HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 143

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

7.1
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling programs to be
debugged in the chip alone, without using an in-circuit emulator. Break conditions that can be set
in the UBC are instruction fetch or data read/write, data size, data content, address value, and stop
timing during instruction fetches.
7.1.1
The features of the user break controller are listed below.
7.1.2
Figure 7.1 shows the logical block diagram of the user break controller.
Two break channels (channel A and channel B). User break interrupts can be requested using
either independent or sequential condition for the two channels (sequential breaks are channel
A, then channel B).
Selection and setting of the following as break compare conditions:
The instruction fetch cycle break can be performed before or after the instruction is executed.
User break trap generated when break conditions are satisfied. A user-designed user break trap
routine can be run.
Address
Data (channel B only, 32-bit maskable)
Bus cycle: Instruction fetch/data access
Read/write
Operand size: byte/word/longword
Selection of 32-bit logical address and ASID to be compared
Address: Compare all bits, mask bottom 10 bits, mask bottom 12 bits. mask all bits
ASID: Compare all bits/mask all bits
Overview
Features
Block Diagram
Section 7 User Break Controller (UBC)
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