HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 194

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bit 6: PSTBY
0
1
9.5
The frequency of the internal clock and peripheral clock can be changed either by changing the
multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of
these are controlled by software through the frequency control register. The methods are described
below. In modes 3–6, the frequency can also be changed by turning PLL circuit 1 on and off, as
described in section 9.6, PLL Standby Function.
9.5.1
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the
4. The processor pauses internally and the WDT starts incrementing. In clock modes 0–2 and 7,
5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins
9.5.2
The WDT will not count unless the multiplication rate is changed simultaneously.
1. In the initial state, IFC1–IFC0 = 00 and PFC1–PFC0 = 10.
2. Set the IFC1, IFC0, PFC1, and PFC0 bits to the new division ratio. The values that can be set
3. The clock is immediately supplied at the new division ratio.
174
WDT. The following must be set:
WTCSR register TME bit = 0: WDT stops
WTCSR register CKS2–CKS0 bits: Division ratio of WDT count clock
WTCNT counter: Initial counter value
IFC1–IFC0 bits and PFC1–PFC0 bits.
the internal and peripheral clocks both stop. In clock modes 3 and 4, only the internal clock
stops. The clock will continue to be output at the CKIO pin as long as the CKOEN bit in the
FRQCR register is set to 1.
operating again. The WDT stops after it overflows.
are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the
wrong value is set, the processor will malfunction.
Changing the Frequency
Changing the Multiplication Rate
Changing the Division Ratio
Description
PLL is not in standby mode.
PLL is in standby mode.
(Initial value)