P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 61

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
13.6.8.3
To ensure the validity of a transmitted message all
receivers perform a CRC check. Therefore, in addition to
the (destuffed) information digits (Start-Of-Frame up to
Data Field), every message includes some control digits
(CRC Sequence; generated by the transmitting
CAN-controller of the respective message) used for error
detection.
The code used by all CAN-controllers is a (shortened)
BCH code, extended by a parity check and has the
following attributes:
As a result, ‘(d 1)’ random errors are detectable (some
exceptions exist).
The CRC Sequence is determined (calculated) by the
following procedure:
1. The destuffed bit stream consisting of Start-Of-Frame
2. This polynomial is divided (modulo-2) by the following
3. The remainder of this polynomial division is the
Burst errors are detected up to a length of 15
least d = 6) are not detected with a residual error
probability of
13.6.8.4
Form Errors result from violations of the fixed form of the
following bit fields:
During the transmission of these bit fields an error
condition is recognized if a dominant bit level instead of a
recessive one is detected.
1996 Jun 27
degree of f(x) . Multiple errors (number of disturbed bits at
127 bits as maximum length of the code.
112 bits as maximum number of information digits
(max. 83 bits are used by the CAN-controller).
Length of the CRC Sequence amounts to 15 bits.
Hamming distance d = 6.
CRC Delimiter
Acknowledge Delimiter
End-Of-Frame
Error Delimiter
Overload Delimiter.
8-bit microcontroller with on-chip CAN
up to the Data Field (if present) is interpreted as
polynomial with coefficients 0 or 1.
generator polynomial, which includes a parity check:
(x + 1) = 1100010110011001 B.
CRC Sequence.
f x ( )
=
CRC Error
Form Error
x
2
14
–
15
+
x
9
3 10
+
x
8
+
–
5
x
6
by CRC check only.
+
x
5
+
x
4
+
x
2
+ +
x
1
61
13.6.8.5
This is detected by a transmitter whenever it does not
monitor a dominant bit during the Acknowledge Slot.
13.6.8.6
The detection of an error is signalled by transmitting an
Error Flag. An Active Error Flag causes a Stuff Error, a Bit
Error or a Form Error at all other CAN-controllers.
13.6.8.7
Errors which occur at all CAN-controllers (global errors)
are 100% detected. For local errors, i.e. for errors
occurring at some CAN-controllers only, the shortened
BCH code, extended by a parity check, has the following
error detection capabilities:
13.6.9
13.6.9.1
A CAN-controller which has too many unsuccessful
transmissions, relative to the number of successful
transmissions, will enter the Bus-OFF state. It remains in
this state, neither receiving nor transmitting messages
until the Reset Request bit is set LOW (absent) and both
Error Counters set to 0 (see Section 13.6.10).
13.6.9.2
A CAN-controller which has received a valid message
correctly, indicates this to the transmitter by transmitting a
dominant bit level on the bus during the Acknowledge Slot,
independent of accepting or rejecting the message.
13.6.9.3
An error-active CAN-controller in its normal operating state
is able to receive and to transmit normally and also to
transmit an Active Error Flag (see Section 13.6.10).
Up to five single Bit Errors are 100% detected, even if
they are distributed randomly within the code.
All single Bit Errors are detected if their total number
(within the code) is odd.
The residual error probability of the CRC check amounts
to (3
CRC check but also by other detection processes
described above the residual error probability is several
magnitudes less than (3
E
10
RROR CONFINEMENT DEFINITIONS
Acknowledgement Error
Error detection by an Error Flag from
another CAN-controller
Error Detection Capabilities
Bus-OFF
Acknowledge
Error-Active
5
). As an error may be detected not only by
10
5
).
Product specification
P8xC592