P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 8

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
6. Pin 55, REF:
7. CAN-bus line:
8. The level of AV
Table 2 Pin description for pins with alternative functions (SOT188-2 and NO330; see note 1)
1996 Jun 27
Port 4
P4.0 to P4.7
Port 1
P1.0 to P1.7
DEFAULT
8-bit microcontroller with on-chip CAN
a) Selection of input resp. output dependent of CAN Control Register bit 5 (CR.5; see Section 13.5.3 Table 32).
b) If the internal reference is used, then REF should be connected to AV
c) After an external reset (RST = HIGH) the internal
d) If the CAN-controller is in the reset state, e.g. after an external reset, then the
a) CRX0 level > CRX1 level is interpreted as a logic 1 (recessive).
b) CRX0 level < CRX1 level is interpreted as a logic 0 (dominant).
during Power-down mode.
CMSR0
CMSR1
CMSR2
CMSR3
CMSR4
CMSR5
CMT0
CMT1
CT0I/INT2
CT1I/INT3
CT2I/INT4
CT3I/INT5
T2
RT2
CTX0
CTX1
SYMBOL
REF+
ALTERNATIVE
must be higher than that of AV
7 to 14
7
8
9
10
11
12
13
14
16 to 21, 23, 24 8-bit quasi-bidirectional I/O port.
16
17
18
19
20
23
24
21
PIN
REF
1
2
8
AV
.
8-bit quasi-bidirectional I/O port.
Compare and Set/Reset outputs for Timer T2.
Compare and toggle outputs for Timer T2.
Capture timer inputs for Timer T2,
or
External interrupt inputs.
T2 event input (rising edge triggered).
T2 timer reset input (rising edge triggered).
CAN transmitter output 0 (note 2).
CAN transmitter output 1 (note 2).
DD
source is activated and, REF is a reference output.
SS
via a capacitor with a value of
DESCRIPTION
1
2
AV
DD
source is switched off
Product specification
P8xC592
10 nF.