P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 62

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
13.6.9.4
An error-passive CAN-controller may transmit or receive
messages normally. In the case of a detected error
condition it transmits a Passive Error Flag instead of an
Active Error Flag. Hence the influence on bus activities by
an error-active CAN-controller (e.g. due to a malfunction)
is reduced.
13.6.9.5
After an error-passive CAN-controller has transmitted a
message, it sends eight recessive bits after the
Intermission Field and then checks for Bus-Idle. If during
Suspend Transmission another CAN-controller starts
transmitting a message the suspended CAN-controller will
become the receiver of this message; otherwise being in
Bus-Idle it may start to transmit a further message.
13.6.9.6
A CAN-controller which either was switched off or in the
Bus-OFF state, must run a Start-Up routine in order to:
13.6.10 A
13.6.10.1 Distinction of short and long disturbances
The CPU must be informed when there are long
disturbances and when bus activities have returned to
normal operation. During long disturbances, a
CAN-controller enters the Bus-OFF state and the CPU
may use default values.
Minor disturbances of bus activities will not effect a
CAN-controller. In particular, a CAN-controller does not
enter the Bus-OFF state or inform the CPU of a short bus
disturbance.
1996 Jun 27
Synchronize with other available CAN-controllers before
starting to transmit. Synchronization is achieved, when
11 recessive bits, equivalent to Acknowledge Delimiter,
End-Of-Frame and Intermission Field, have been
detected (Bus-Free).
Wait for other CAN-controllers without passing into the
Bus-OFF state (due to a missing acknowledge), if there
is no other CAN-controller currently available.
8-bit microcontroller with on-chip CAN
IMS OF ERROR CONFINEMENT
Error-Passive
Suspend Transmission
Start-Up
62
13.6.10.2 Detection and localization of hardware
The rules for error confinement are defined by the
CAN-protocol specification (and implemented in the
P8xC592's on-chip CAN-controller), in such a way that the
CAN-controller, being nearest to the error-locus, reacts
with a high probability the quickest (i.e. becomes
error-passive or Bus-OFF). Hence errors can be localized
and their influence on normal bus activities is minimized.
13.6.10.3 Error Confinement
All CAN-controllers contain a Transmit Error Counter and
a Receive Error Counter, which registers errors during the
transmission and the reception of messages, respectively.
If a message is transmitted or received correctly, the count
is decreased. In the event of an error, the count is
increased. The Error Counters have an non-proportional
method of counting: an error causes a larger counter
increase than a correctly transmitted/received message
causes the count to decrease. Over a period of time this
may result in an increase in error counts, even if there are
fewer corrupted messages than uncorrupted ones. The
level of the Error Counters reflect the relative frequency of
disturbances. The ratio of increase/decrease depends on
the acceptable ratio of invalid/valid messages on the bus
and is hardware implemented to eight.
If one of the Error Counters exceeds the Warning Limit of
96 error points, indicating a significant accumulation of
error conditions, this is signalled by the CAN-controller
(Error Status, Error Interrupt).
A CAN-controller operates in the error-active mode until it
exceeds 127 error points on one of its Error Counters. At
this value it will enter the error-passive state. A transmit
error which exceeds 255 error points results in the
CAN-controller entering the Bus-OFF state.
disturbances and defects
Product specification
P8xC592