P80C592FFA/00,512 NXP Semiconductors, P80C592FFA/00,512 Datasheet - Page 68

• Manufacturer Part Number: P80C592FFA/00,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C592FFA/00,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 48
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1241-5; 935086530512; P80C592FFAA

Philips Semiconductors
15.1
Table 80 Power Control Register (address 87H)
Table 81 Description of the PCON bits
Note
1. If PD and IDL are set to HIGH at the same time, PD takes precedence. The reset value of PCON is 0XX00000B.
15.2
In order to reduce power consumption of the P8xC592 the
CAN-controller may be switched off (disconnecting the
internal clock) by setting the CAN Command Register bit 4
(Sleep) HIGH. The CAN-controller leaves this Sleep mode
by detecting either activity on the CAN-bus (dominant
bit-level on CRX0/CRX1; see Chapter 5, Table 1) or by
setting the Sleep bit to LOW. As the CPU can not only write
to the Sleep bit, but can also read it, the CAN-controller
status can be determined directly.
15.3
The instruction that sets bit PCON.0 to HIGH is the last
one executed in the normal operating mode before Idle
mode is activated.
Once in the Idle mode, the CPU status is preserved in its
entirety: the Stack Pointer, Program Counter, Program
Status Word, Accumulator, RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in see Table 82.
1996 Jun 27
8-bit microcontroller with on-chip CAN
SMOD
BIT
7
7
6
5
4
3
2
1
0
Power Control Register (PCON)
CAN Sleep Mode
Idle Mode
SMOD
WLE
GF1
GF0
PD
IDL
SYMBOL
6
Double baud rate bit. When set to logic 1 the baud rate is doubled when the serial port
SIO0 is being used in Modes 1, 2 and 3.
Reserved.
Watchdog Load Enable. This flag must be set by software prior to loading T3
(Watchdog timer). It is cleared when T3 is loaded.
General purpose flag bits.
Power-down bit. Setting this bit activates Power-down mode (note 1). It can only be set
if input EW is HIGH.
Idle mode bit. Setting this bit activates the Idle mode (note 1).
5
WLE
4
68
There are three ways to terminate the Idle mode:
Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware, provided that the interrupt
source is active during Idle mode. After the interrupt is
serviced, the program continues with the instruction
immediately after the one, at which the interrupt request
was detected.
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear
one or both flag bits. When Idle mode is terminated by
an interrupt, the service routine can examine the status
of the flag bits.
Another way of terminating the Idle mode is an external
hardware reset. Since the oscillator is still running, the
reset signal is required to be active only for two machine
cycles (24 oscillator periods) to complete the reset
operation.
The third way is the internally generated watchdog reset
after an overflow of Timer 3.
GF1
3
FUNCTION
GF0
2
PD
1
Product specification
P8xC592
IDL
0