MC908QY4ACDWE Freescale Semiconductor, MC908QY4ACDWE Datasheet

IC MCU 8BIT 4K FLASH 16-SOIC

MC908QY4ACDWE

Manufacturer Part Number
MC908QY4ACDWE
Description
IC MCU 8BIT 4K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QY4ACDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details

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MC68HC908QY4A
MC68HC908QT4A
MC68HC908QY2A
MC68HC908QT2A
MC68HC908QY1A
MC68HC908QT1A
Data Sheet
M68HC08
Microcontrollers
MC68HC908QY4A
Rev. 3
03/2010
freescale.com

MC908QY4ACDWE Summary of contents

Page 1

MC68HC908QY4A MC68HC908QT4A MC68HC908QY2A MC68HC908QT2A MC68HC908QY1A MC68HC908QT1A Data Sheet M68HC08 Microcontrollers MC68HC908QY4A Rev. 3 03/2010 freescale.com ...

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...

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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2007–2010. All rights reserved. ...

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... Corrected clock source. — Updated maximum values for SI — Changed CGMXCLK to — Added note 6 below table MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Number(s) — Corrected DD — Corrected clock source. — Renamed ADCSC — Updated 27, 30, 31, 34, 95, Freescale Semiconductor Page N 103 121 165 ...

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... Chapter 12 Input/Output Ports (PORTS 103 Chapter 13 System Integration Module (SIM 109 Chapter 14 Timer Interface Module (TIM 125 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 171 Appendix A 908QTA/QYxA Conversion Guidelines 191 Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev ...

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... List of Chapters 6 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 MC68HC908QYA/QTA Family Data Sheet, Rev ...

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... SSA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 REFL Chapter 4 Auto Wakeup Module (AWU) Chapter 5 Configuration Register (CONFIG) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

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... CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2 Features 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.1 MODE = 8.3.2 MODE = Freescale Semiconductor Chapter 6 Computer Operating Properly (COP) Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) MC68HC908QYA/QTA Family Data Sheet, Rev ...

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... Forced Reset Operation 10.3.3 LVI Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.4 LVI Trip Selection 10.4 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10 Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Voltage Inhibit (LVI) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Port A Summary Table 106 12.4 Port 106 12.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.4.2 Data Direction Register 107 12.4.3 Port B Input Pullup Enable Register 108 12.4.4 Port B Summary Table 108 Freescale Semiconductor Chapter 11 Oscillator (OSC) Module Chapter 12 Input/Output Ports (PORTS) MC68HC908QYA/QTA Family Data Sheet, Rev ...

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... Break Flag Control Register 123 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.2 Features 125 14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12 Chapter 13 System Integration Module (SIM) Chapter 14 Timer Interface Module (TIM) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.3.1.6 Baud Rate 150 15.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Freescale Semiconductor Chapter 15 Development Support MC68HC908QYA/QTA Family Data Sheet, Rev ...

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... Keyboard Interface Module (KBI) Functionality 195 A.2.5.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 A.2.6 On-Chip Routine Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 A.3 Conversion Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 A.4 Code Changes Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 A.5 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 A.6 Differences in Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14 Chapter 16 Electrical Specifications Chapter 17 Appendix A MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Monitor ROM containing user callable program/erase routines (2) – FLASH security 1. See 16.11 Oscillator Characteristics 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor 0.4 FLASH Memory Size 1536 bytes 1536 bytes 6 channel, 10 bit 4096 bytes ...

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... Memory-to-memory data transfers Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 16 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

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... BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Freescale Semiconductor M68HC08 CPU MC68HC908QY4A 4096 BYTES USER FLASH V DD ...

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... PTA1/TCH1/AD1/KBI1 PTB5 6 11 PTB2 PTB4 7 10 PTB3 9 PTA2/IRQ/KBI2/TCLK 8 16-PIN ASSIGNMENT 1 16 PTA1/TCH1/AD1/KBI1 2 15 PTB2 3 14 PTB3 V PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTB7 PTB4 7 10 PTB5 PTB6 8 9 PTA4/OSC2/AD2/KBI4 16-PIN ASSIGNMENT 1 8 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 8-PIN ASSIGNMENT MC68HC908QT2A AND MC68HC908QT4A DFN Freescale Semiconductor ...

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... PTB1 — General-purpose I/O port (1) PTB1 AD5 — A/D channel 5 input PTB2- 6 General-purpose I/O port (1) PTB7 1. The PTB pins are not available on the 8-pin packages. Freescale Semiconductor Table 1-2. Pin Functions Description MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Pin Functions Input/Output Power Power Input/Output ...

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... AD1 → TCH1 → KBI1 → PTA1 IRQ → TCLK → KBI2 → PTA2 RST → KBI3 → PTA3 OSC2 → AD2 → KBI4 → PTA4 OSC1 → AD3 → KBI5 → PTA5 AD4 → PTB0 AD5 → PTB1 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Registers between $0100 and $FFFF require non-direct page addressing modes. See addressing modes. Freescale Semiconductor Chapter 7 Central Processor Unit (CPU) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Figure ...

Page 22

... USER VECTORS ↓ 48 BYTES $FFFF MC68HC908QY4A, MC68HC908QT4A Memory Map 22 Figure 2-1. Memory Map MC68HC908QYA/QTA Family Data Sheet, Rev. 3 RESERVED 2560 BYTES FLASH MEMORY 1536 BYTES MC68HC908QT1A, MC68HC908QT2A, MC68HC908QY1A, and MC68HC908QY2A Memory Map Freescale Semiconductor $EE00 ↓ $F7FF $F800 ↓ $FDFF ...

Page 23

... Keyboard Interrupt $001B Enable Register (KBIER) Write: See page 88. Reset: Read: Keyboard Interrupt Polarity $001C Register (KBIPR) Write: See page 88. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit AWUL R PTA5 Unaffected by reset PTB7 PTB6 PTB5 Unaffected by reset R R ...

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... Bit 3 Bit 2 Bit Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit ELS0B ELS0A TOV0 Bit 11 Bit 10 Bit 9 Bit 4 Bit 3 Bit 2 Bit Reserved U = Unaffected Freescale Semiconductor Bit 0 MODE 0 RSTEN (2) 0 COPD 0 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 Bit 0 ...

Page 25

... Reset: Read: ADC10 Data Register Low $003E (ADRL) Write: See page 48. Reset: Read: ADC10 Clock Register $003F (ADCLK) Write: See page 48. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit CH1F 0 CH1IE MS1A Bit 15 Bit 14 Bit 13 Bit 12 Indeterminate after reset ...

Page 26

... SBSW ILOP ILAD MODRST LVI IF3 IF2 IF1 IF11 IF10 IF9 IF8 IF19 IF18 IF17 IF16 HVEN MASS ERASE Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Reserved U = Unaffected Freescale Semiconductor Bit BDCOP IF7 R 0 IF15 R 0 PGM 0 Bit 8 0 Bit ...

Page 27

... Reset: Read: Internal Oscillator Trim $FFC1 (Factory Programmed Write: VDD = 5.0 V) Reset: Read: COP Control Register $FFFF (COPCTL) Write: See page 63. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit LVIOUT BPR7 BPR6 BPR5 BPR4 Unaffected by reset TRIM7 ...

Page 28

... TIM overflow vector IF4 $FFF4,5 TIM channel 1 vector IF3 $FFF6,7 TIM channel 0 vector IF2 — Not used IF1 $FFFA,B IRQ vector — $FFFC,D SWI vector — $FFFE,F Reset vector ;point one past RAM ;SP<-(H:X-1) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Vector Freescale Semiconductor ...

Page 29

... This read/write bit configures the memory for mass erase operation Mass erase operation selected 0 = Mass erase operation unselected 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor supply. The program and erase operations are DD NOTE 6 ...

Page 30

... FLASH memory. While these operations must be performed in the order as shown, other unrelated operations may occur between the steps. A page erase of the vector page will erase the internal oscillator trim values at $FFC0 and $FFC1. 30 NOTE NOTE CAUTION MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 31

... Write any data to any FLASH location within the address range desired. 4. Wait for a time NVS 5. Set the HVEN bit. 1. When in monitor mode, with security sequence failed (see stead of any FLASH address. Freescale Semiconductor (1) within the FLASH memory address range. NOTE NOTE CAUTION NOTE 15 ...

Page 32

... PGM bit, must not exceed the maximum programming time (1) NOTE NOTE PROG NOTE Register. Once the FLBPR is programmed with a value other than , present on the IRQ pin. This voltage also TST maximum. PROG MC68HC908QYA/QTA Family Data Sheet, Rev maximum, see 16.15 Freescale Semiconductor ...

Page 33

... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS ...

Page 34

... FLBPR, internal oscillator trim values, and vectors are protected The entire FLASH memory is not protected. MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 BPR2 BPR1 BPR0 Freescale Semiconductor ...

Page 35

... AN2346 — EEPROM Emulation Using FLASH in MC68HC908QY/QT MCUs AN2690 — Low Frequency EEPROM Emulation on the MC68HC908QY4 An EEPROM emulation driver, available at www.freescale.com, has been developed and qualified: AN3040 — M68HC08 EEPROM Emulation Driver Freescale Semiconductor . Hence, item 2 listed above is already taken HV MC68HC908QYA/QTA Family Data Sheet, Rev. 3 ...

Page 36

... Memory 36 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 37

... REFH a 8-bit representation. If ADVIN is equal to or less than V Input voltages between V REFH Input voltage must not exceed the analog supply voltages. Freescale Semiconductor REFL and V are straight-line linear conversions. REFL NOTE MC68HC908QYA/QTA Family Data Sheet, Rev ...

Page 38

... M68HC08 CPU MC68HC908QY4A 4096 BYTES USER FLASH MC68HC908QYA/QTA Family Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

Page 39

... The bus clock — This clock source is equal to the bus frequency. This clock is selected when ADICLK is high and ACLKEN is low. Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If the available clocks are too slow, the ADC10 will not perform according to specifications. If the available Freescale Semiconductor ADCLK ADCK CLOCK ...

Page 40

... When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but continue to be the values transferred after the completion of the last successful conversion. In the case that the conversion was aborted by a reset, ADRH and ADRL return to their reset states. 40 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 41

... MHz, then the conversion time for a single 10-bit conversion is: Maximum Conversion time = Number of bus cycles = 11.25 μ MHz = 45 cycles The ADCK frequency must be between f maximum to meet A/D specifications. Freescale Semiconductor ACLKEN 0 1 ≥ ...

Page 42

... DDA SSA at a quiet point in the ground plane. SS noise but will increase effective conversion time DD MC68HC908QYA/QTA Family Data Sheet, Rev kept below (4096*I ) for less than ADVIN Leak (if available). (if available (if available). This will REFL SSA , one-time error. LSB Freescale Semiconductor ) is high. ...

Page 43

... LSB • Missing codes are those which are never converted for any input value. In 8-bit or 10-bit mode, the ADC10 is guaranteed to be monotonic and to have no missing codes. Freescale Semiconductor – LSB REFH REFL 10-bit mode ...

Page 44

... To protect status bits during the break state, write BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the 44 sheet. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 45

... In some packages, REFL V is connected internally to V REFL potential There will be a brief current associated with V SSA Freescale Semiconductor ) DDA as its power pin. In some packages, V DDA pin to the same voltage potential as V DDA for good results. ...

Page 46

... ADSCR. Any write to ADSCR with ADCO set and the ADCH bits not all 1s will abort the current conversion and begin continuous conversions. 46 pin to the same potential as V REFL AIEN ADCO ADCH4 ADCH3 MC68HC908QYA/QTA Family Data Sheet, Rev the single point SSA 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor . SSA ...

Page 47

... ADRL is read. If ADRL is not read until the after next conversion is completed, then the intermediate conversion result will be lost. In 8-bit mode, this register contains no interlocking with ADRL. Freescale Semiconductor 3-2. The successive approximation converter subsystem is turned off Table 3-2. Input Channel Select ...

Page 48

... Low-power configuration: The power is reduced at the expense of maximum clock speed High-speed configuration AD6 AD5 AD4 AD3 ADIV0 ADICLK MODE1 MC68HC908QYA/QTA Family Data Sheet, Rev Bit Bit 0 0 AD9 AD8 Bit 0 AD2 AD1 AD0 Bit 0 MODE0 ADLSMP ACLKEN Freescale Semiconductor ...

Page 49

... The asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion ADICLK specifies the input clock source and conversions will not continue in stop mode Freescale Semiconductor Table 3-3. ADC10 Clock Divide Ratio ADIV0 Divide Ratio (ADIV) ...

Page 50

... Analog-to-Digital Converter (ADC10) Module 50 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 51

... Exit from low-power stop mode without external signals • Selectable timeout periods • Dedicated low-power internal oscillator separate from the main system clock sources • Option to allow bus clock source to run the AWU if enabled in STOP Freescale Semiconductor AUTOWUGEN DIV 2 SHORT DIV 2 ...

Page 52

... AWU Latch (AWUL) — The AWUL bit is set when the AWU counter overflows. The auto wakeup interrupt mask bit, AWUIE, is used to enable or disable AWU interrupt requests. The AWU shares its interrupt with the KBI vector. 52 4-1. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Figure 4-1 applied Figure 4-1) has no effect on AWUL Freescale Semiconductor ...

Page 53

... There is no PTA6 port or any of the associated bits such as PTA6 data direction or pullup bits Auto wakeup interrupt request is pending 0 = Auto wakeup interrupt request is not pending PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Freescale Semiconductor PTA5 ...

Page 54

... Bit 7 Read: 0 AWUIE Write: Reset Unimplemented Figure 4-4. Keyboard Interrupt Enable Register (KBIER KEYF NOTE 9.8.1 Keyboard Status and Control Register KBIE5 KBIE4 KBIE3 MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...

Page 55

... The configuration register 1 (CONFIG1), is used to select the period for the AWU. The timeout will be based on the COPRS bit along with the clock source for the AWU. Bit 7 Read: COPRS Write: 0 Reset: POR Unaffected Figure 4-6. Configuration Register 1 (CONFIG1) Freescale Semiconductor NOTE 9.8.2 Keyboard Interrupt Enable ...

Page 56

... Stop mode recovery after 32 BUSCLKX4 cycles 0 = Stop mode recovery after 4096 BUSCLKX4 cycles LVISTOP, LVIRST, LVIPWRD, LVITRIP, and COPD bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see Chapter 5 Configuration Register (CONFIG) 56 NOTE MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 57

... The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 Bit 7 6 Read: IRQPUD IRQEN Write: Reset POR Reserved Figure 5-1. Configuration Register 2 (CONFIG2) Freescale Semiconductor NOTE and Figure 5- Unaffected MC68HC908QYA/QTA Family Data Sheet, Rev. 3 ...

Page 58

... LVI disabled during stop mode LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module LVI module resets disabled 0 = LVI module resets enabled 58 DD NOTE LVIRSTD LVIPWRD LVITRIP MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 SSREC STOP COPD Freescale Semiconductor ...

Page 59

... STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module COP module disabled 0 = COP module enabled Freescale Semiconductor for the LVI’s voltage trip points for each of the modes. DD NOTE NOTE MC68HC908QYA/QTA Family Data Sheet, Rev. 3 ...

Page 60

... Configuration Register (CONFIG) 60 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 61

... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 13 System Integration Module (SIM) Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details. ...

Page 62

... The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Chapter 5 Configuration Register 62 NOTE NOTE Figure (CONFIG). MC68HC908QYA/QTA Family Data Sheet, Rev. 3 13.8.1 SIM Reset Status 6-1. Figure 6-2) clears the COP counter and Freescale Semiconductor Register. ...

Page 63

... The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Bit 7 Read: Write: Reset: Figure 6-2. COP Control Register (COPCTL) Freescale Semiconductor (CONFIG). is present on the IRQ pin. TST ...

Page 64

... Computer Operating Properly (COP) 64 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 65

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev ...

Page 66

... CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H:X) MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...

Page 67

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: Freescale Semiconductor ...

Page 68

... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result NOTE MC68HC908QYA/QTA Family Data Sheet, Rev Bit Freescale Semiconductor ...

Page 69

... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Arithmetic/Logic Unit (ALU) ...

Page 70

... REL – – – – – – REL 90 ⊕ – – – – – – REL 92 – – – – – – REL 28 – – – – – – REL 29 – – – – – – REL 22 Freescale Semiconductor ...

Page 71

... Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? IRQ = 1 PC ← (PC rel ? IRQ = 0 (A) & (M) PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ⊕ ...

Page 72

... INH 4A INH 5A – – – IX1 SP1 9E6A ff – – – – INH 52 IMM A8 ii DIR B8 dd EXT IX2 – – – IX1 SP1 9EE8 ff SP2 9ED8 ee ff DIR 3C dd INH 4C INH 5C – – – IX1 SP1 9E6C ff Freescale Semiconductor ...

Page 73

... ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack Freescale Semiconductor Description PC ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Unconditional Address A ← (M) H:X ← (M ← (M) ...

Page 74

... IX1 SP1 9EE7 SP2 9ED7 0 – – – DIR 35 – – 0 – – – INH 8E DIR BF EXT CF IX2 DF 0 – – – IX1 SP1 9EEF SP2 9EDF IMM A0 DIR B0 EXT C0 IX2 D0 – – IX1 SP1 9EE0 SP2 9ED0 Freescale Semiconductor ...

Page 75

... M Memory location N Negative bit 7.8 Opcode Map See Table 7-2. Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...

Page 76

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 77

... The external IRQ pin is falling edge sensitive out of reset and is software-configurable to be either falling edge or falling edge and low level sensitive. The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin. Freescale Semiconductor for more information on enabling the IRQ pin. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 ...

Page 78

... MC68HC908QY4A 4096 BYTES USER FLASH NOTE MC68HC908QYA/QTA Family Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

Page 79

... The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMASK, which makes it useful in applications where polling is preferred. When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. Freescale Semiconductor V DD CLR ...

Page 80

... The IRQ module does not share its pin with any module on this MCU. 8.7.1 IRQ Input Pins (IRQ) The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup device. 80 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 sheet. Freescale Semiconductor ...

Page 81

... Writing this read/write bit disables the IRQ interrupt request IRQ interrupt request disabled 0 = IRQ interrupt request enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only Freescale Semiconductor ...

Page 82

... External Interrupt (IRQ) 82 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 83

... If the keyboard interrupt is edge and level sensitive, an interrupt request is present as long as any enabled keyboard interrupt input is asserted. Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Figure 9-1 for port location Figure 9-2 ...

Page 84

... M68HC08 CPU MC68HC908QY4A 4096 BYTES USER FLASH MC68HC908QYA/QTA Family Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

Page 85

... IMASKK, which makes it useful in applications where polling is preferred. Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must for software to read the pin. Freescale Semiconductor V DD CLR D ...

Page 86

... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 86 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 sheet. Freescale Semiconductor ...

Page 87

... Writing this read/write bit prevents the output of the KBI latch from generating interrupt requests Keyboard interrupt requests disabled 0 = Keyboard interrupt requests enabled MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins Keyboard interrupt requests on edge and level 0 = Keyboard interrupt requests on edge only Freescale Semiconductor ...

Page 88

... Keyboard polarity is high level and/or rising edge 0 = Keyboard polarity is low level and/or falling edge KBIE5 KBIE4 KBIE3 NOTE Chapter 4 Auto Wakeup Module KBIP5 KBIP4 KBIP3 MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 KBIE2 KBIE1 KBIE0 (AWU Bit 0 KBIP2 KBIP1 KBIP0 Freescale Semiconductor ...

Page 89

... LVI module. LVISTOP, LVIPWRD, LVITRIP, and LVIRSTD are user selectable options found in the configuration register FROM CONFIGURATION REGISTER LOW V DD DETECTOR LVITRIP FROM CONFIGURATION REGISTER Freescale Semiconductor Chapter 5 Configuration Register STOP INSTRUCTION FROM CONFIGURATION REGISTER LVIRSTD LVIPWRD > TRIPR ≤ ...

Page 90

... TRIPR TRIPF NOTE MC68HC908QYA/QTA Family Data Sheet, Rev. 3 operating range. The actual DD and 16.8 3-V DC Electrical DD . See Chapter 13 System TRIPR ) for the higher V TRIPF level, software can monitor V DD rises above the rising trip point voltage, Freescale Semiconductor must polling HYS ...

Page 91

... The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset is disabled. Bit 7 Read: LVIOUT Write: Reset Unimplemented Figure 10-2. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when the V when V voltage rises above Freescale Semiconductor voltage falls below the V DD ...

Page 92

... Low-Voltage Inhibit (LVI) 92 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 93

... The oscillator contains these major subsystems: • Internal oscillator circuit • Internal or external clock switch control • External clock circuit • External crystal circuit • External RC clock circuit Freescale Semiconductor for information on PTAPUEN register. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Figure 11-1 for port 93 ...

Page 94

... M68HC08 CPU MC68HC908QY4A 4096 BYTES USER FLASH MC68HC908QYA/QTA Family Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

Page 95

... All devices are factory programmed with trim values that are stored in FLASH memory at locations $FFC0 and $FFC1. The trim value is not automatically loaded into the OSCTRIM register. User software must Freescale Semiconductor Figure 11-2 shows only the logical relation of XTALCLK to OSC1 ...

Page 96

... In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 11-2. This figure shows only the logical representation of the internal components and may not represent actual circuitry. 96 11.8.1 Oscillator Status and Control MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Register. Freescale Semiconductor ...

Page 97

... Refer to the oscillator characteristics table in the Electricals section for more information. SIMOSCEN (INTERNAL SIGNAL) OR OSCENINSTOP (BIT LOCATED IN CONFIGURATION REGISTER) MCU OSC1 Figure 11-2. XTAL Oscillator External Connections Freescale Semiconductor NOTE ) is included in the diagram to follow strict Pierce S BUSCLKX4 XTALCLK ÷ 2 OSC2 ...

Page 98

... OSC2 — AVAILABLE FOR ALTERNATIVE PIN FUNCTION See the electricals section for component value. MC68HC908QYA/QTA Family Data Sheet, Rev provide a clock source with EXT 11-3. value must have a tolerance of EXT . RCCLK OSCOPT = EXTERNAL RC SELECTED BUSCLKX2 BUSCLKX4 ÷ 2 ALTERNATIVE PIN FUNTION OSC2EN Freescale Semiconductor ...

Page 99

... RC, the OSC2 pin can be used to output BUSCLKX4. Option XTAL oscillator External clock Internal oscillator or RC oscillator Freescale Semiconductor Table 11-1. OSC2 Pin Function OSC2 Pin Function Inverting OSC1 General-purpose I/O or alternative pin function Controlled by OSC2EN bit OSC2EN = 0: General-purpose I/O or alternative pin function OSC2EN = 1: BUSCLKX4 output MC68HC908QYA/QTA Family Data Sheet, Rev ...

Page 100

... External oscillator clock 0 External RC 1 External crystal (range selected using ECFSx bits) ICFS0 Internal Clock Frequency 0 4.0 MHz 1 8.0 MHz 0 12.8 MHz — default reset condition 1 Reserved MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 ECGST ECFS0 ECGON 11.3.2.2 Internal to External Freescale Semiconductor ...

Page 101

... The oscillator period is based on the oscillator frequency selected by the ICFS bits in OSCSC. Applications using the internal oscillator should copy the internal oscillator trim value at location $FFC0 or $FFC1 into this register to trim the clock source. Freescale Semiconductor ECFS0 External Crystal Frequency 0 8 MHz – ...

Page 102

... Oscillator (OSC) Module 102 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 103

... In this case, the BIH and BIL instructions can be used to read the logic level on the PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. Freescale Semiconductor ...

Page 104

... PTA5 PTA4 PTA3 Unaffected by reset Figure 12-1. Port A Data Register (PTA) Chapter 4 Auto Wakeup Module DDRA5 DDRA4 DDRA3 Unimplemented NOTE MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 PTA2 PTA1 PTA0 (AWU)). There is no PTA6 2 1 Bit 0 0 DDRA1 DDRA0 Freescale Semiconductor ...

Page 105

... These read/write bits are software programmable to enable pullup devices on port A pins Corresponding port A pin configured to have internal pullup if its DDRA bit is set Pullup device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit Freescale Semiconductor DDRAx RESET PTAx Figure 12-3. Port A I/O Circuit ...

Page 106

... DDRA5–DDRA0 Module PTB6 PTB5 PTB4 PTB3 Unaffected by reset Figure 12-5. Port B Data Register (PTB) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Accesses to PTA Read Write Pin PTA5–PTA0 Pin PTA5–PTA0 PTA5–PTA0 PTA5–PTA0 Chapter Bit 0 PTB2 PTB1 PTB0 Freescale Semiconductor (3) (3) (5) ...

Page 107

... WRITE DDRB WRITE PTB READ PTB When DDRBx reading PTB reads the PTBx data latch. When DDRBx reading PTB reads the logic level on the PTBx pin. The data latch can always be written, regardless of the state of its data direction bit. Freescale Semiconductor DDRB5 ...

Page 108

... Writing affects data register, but does not affect the input. 108 PTBPUE5 PTBPUE4 PTBPUE3 Table 12-2. Port B Pin Functions Accesses to DDRB Read/Write (2) DDRB7–DDRB0 DDRB7–DDRB0 MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 PTBPUE2 PTBPUE2 PTBPUE0 Accesses to PTB Read Write Pin PTB7–PTB0 Pin PTB7–PTB0 Freescale Semiconductor (3) ...

Page 109

... R/W 13.2 RST and IRQ Pins Initialization RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be activated by programing CONFIG2 accordingly. Refer to Freescale Semiconductor Figure Table 13-1. Signal Name Conventions Description Buffered clock from the internal XTAL oscillator circuit. ...

Page 110

... BUSCLKX2 (FROM OSCILLATOR) INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) FORCED MON MODE ENTRY (FROM MENRST MODULE) INTERRUPT SOURCES CPU INTERFACE Figure 13-2. BUS CLOCK GENERATORS Freescale Semiconductor ...

Page 111

... RL if the RSTEN bit is set in the CONFIG2 register. BUSCLKX2 RST ADDRESS BUS PC Freescale Semiconductor 13.7.2 Stop 13.5 SIM Counter), but an external reset does not. Each of shows the relative timing. The RST pin function is only available Figure 13-3. External Reset Timing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Reset and System Initialization Mode ...

Page 112

... CYCLES Figure 13-4. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET POR LVI Figure 13-5. Sources of Internal Reset Table 13-2. Reset Recovery Timing Actual Number of Cycles 4163 (4096 + MC68HC908QYA/QTA Family Data Sheet, Rev. 3 VECTOR HIGH 67 ( Freescale Semiconductor ...

Page 113

... The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). 13.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. Freescale Semiconductor 4096 32 32 CYCLES ...

Page 114

... LVI trip voltage V DD rises above V DD 13.7.2 Stop Mode 13.4.2 Active Resets from Internal Sources MC68HC908QYA/QTA Family Data Sheet, Rev. 3 for memory ranges. . The LVI TRIPF . Sixty-four BUSCLKX4 TRIPR for details.) The SIM counter is for counter control and Freescale Semiconductor ...

Page 115

... If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. Freescale Semiconductor shows interrupt recovery timing. NOTE MC68HC908QYA/QTA Family Data Sheet, Rev. 3 ...

Page 116

... I BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 13-7. Interrupt Processing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 STACK CPU REGISTERS SET I BIT UNSTACK CPU REGISTERS EXECUTE INSTRUCTION Freescale Semiconductor ...

Page 117

... I BIT ADDRESS BUS DUMMY SP DATA BUS DUMMY R/W MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS R/W INT1 INT2 Figure 13-10 Freescale Semiconductor SP – – – – – 1[7:0] PC – 1[15: Figure 13-8 Interrupt Entry SP – – – 1 CCR – 1[7:0] PC – 1[15:8] OPCODE Figure 13-9 ...

Page 118

... IMASK IF1 $FFFA–$FFFB CH0IE IF3 $FFF6–$FFF7 CH1IE IF4 $FFF4–$FFF5 TOIE IF5 $FFF2–$FFF3 IMASKK IF14 $FFE0–$FFE1 AIEN IF15 $FFDE–$FFDF Freescale Semiconductor ...

Page 119

... Interrupt Status Register 3 Bit 7 Read: IF22 Write: R Reset Reserved Figure 13-13. Interrupt Status Register 3 (INT3) IF15–I 22 — Interrupt Flags F These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Freescale Semiconductor IF5 IF4 IF3 IF2 ...

Page 120

... Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. 120 Support.) The SIM puts the CPU into the break WAIT ADDR + 1 PREVIOUS DATA NEXT OPCODE Figure 13-14. Wait Mode Entry Timing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Figure 13-14 SAME SAME SAME SAME Freescale Semiconductor shows ...

Page 121

... This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time by clearing the SSREC bit. Freescale Semiconductor show the timing for wait recovery. $6E0B $6E0C ...

Page 122

... NEXT OPCODE Figure 13-17. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP +1 STOP + 2 STOP + PIN COP ILOP ILAD MC68HC908QYA/QTA Family Data Sheet, Rev. 3 shows stop mode entry timing and SAME SAME SAME SP SP – – – Bit 0 MODRST LVI Freescale Semiconductor ...

Page 123

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Freescale Semiconductor ...

Page 124

... System Integration Module (SIM) 124 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 125

... The TIM clock source is one of the seven prescaler outputs or the external clock input pin, TCLK if available. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the clock source. Freescale Semiconductor Figure 14-1 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 ...

Page 126

... M68HC08 CPU MC68HC908QY4A 4096 BYTES USER FLASH MC68HC908QYA/QTA Family Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE Freescale Semiconductor ...

Page 127

... When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at Freescale Semiconductor PRESCALER SELECT PS2 ...

Page 128

... TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000. See 128 NOTE OVERFLOW PERIOD PULSE WIDTH OUTPUT COMPARE 14.8.1 TIM Status and Control MC68HC908QYA/QTA Family Data Sheet, Rev. 3 OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Register. Freescale Semiconductor ...

Page 129

... TCH1, is available as a general-purpose I/O pin. In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active Freescale Semiconductor NOTE NOTE MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Functional Description 14 ...

Page 130

... The result duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 14.8.1 TIM Status and Control 130 NOTE Register. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Table 14-2. Table 14-2. Freescale Semiconductor ...

Page 131

... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Interrupts sheet ...

Page 132

... Clear TOF by reading the TSC register when TOF is set and then writing TOF. 132 The minimum TCLK pulse width is specified in the Timer Interface TOIE TSTOP TRST MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Figure 14-1 for the port pins 14.8 Bit 0 PS2 PS1 PS0 Freescale Semiconductor ...

Page 133

... Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the counter as Table 14-1 shows. PS2 Freescale Semiconductor NOTE NOTE Table 14-1. Prescaler Selection PS1 PS0 TIM Clock Source Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ ...

Page 134

... Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit Bit14 Bit13 Bit12 Bit11 Bit6 Bit5 Bit4 Bit3 NOTE MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit10 Bit9 Bit8 Bit 0 Bit2 Bit1 Bit0 Freescale Semiconductor ...

Page 135

... CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIM interrupt service requests on channel Channel x interrupt requests enabled 0 = Channel x interrupt requests disabled MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TSC0. Freescale Semiconductor MS0B ...

Page 136

... Capture on rising or falling edge 0 Software compare only 1 Toggle output on compare Output compare or PWM 0 Clear output on compare 1 Set output on compare 1 Toggle output on compare Buffered output 0 compare or Clear output on compare buffered PWM 1 Set output on compare NOTE MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Configuration Freescale Semiconductor ...

Page 137

... Write: Reset: Figure 14-12. TIM Channel x Register High (TCHxH) Bit 7 Read: Bit 7 Write: Reset: Figure 14-13. TIM Channel Register Low (TCHxL) Freescale Semiconductor NOTE shows, the CHxMAX bit takes effect in the cycle after it is set OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Figure 14-11 ...

Page 138

... Timer Interface Module (TIM) 138 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 139

... BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev. 3 139 ...

Page 140

... BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] MC68HC908QYA/QTA Family Data Sheet, Rev. 3 CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE BKPT CONTROL (TO SIM) Freescale Semiconductor ...

Page 141

... Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) Freescale Semiconductor CAUTION 13.8.2 Break Flag Control Register MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Break Module (BRK) and the Break Interrupts subsection 141 ...

Page 142

... Figure 15-4. Break Address Register High (BRKH) Bit 7 Read: Bit 7 Write: Reset: 0 Figure 15-5. Break Address Register Low (BRKL) 142 Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit MC68HC908QYA/QTA Family Data Sheet, Rev Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...

Page 143

... Wait mode was not exited by break interrupt 15.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU break state. Bit 7 Read: BCFE Write: Reset Reserved R Figure 15-8. Break Flag Control Register (BFCR) Freescale Semiconductor ...

Page 144

... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 144 ( reset vector is blank ($FFFE and $FFFF contain TST is applied to IRQ TST show example circuits used to enter monitor mode and communicate with MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Figure 15-10, Freescale Semiconductor ...

Page 145

... PTA0 = 1, FROM Table 15-1 RESET VECTOR BLANK? YES FORCED MONITOR MODE DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) Figure 15-9. Simplified Monitor Mode Entry Flowchart Freescale Semiconductor POR RESET YES NO IRQ = V ? TST NO NORMAL USER MODE HOST SENDS 8 SECURITY BYTES YES IS RESET POR? ...

Page 146

... MC68HC908QYA/QTA Family Data Sheet, Rev RST (PTA3) OSC1 (PTA5) PTA1 IRQ (PTA2) PTA4 PTA0 Value not critical N.C. RST (PTA3 OSC1 (PTA5) * PTA1 IRQ (PTA2) PTA4 PTA0 Value not critical Freescale Semiconductor V DD 0.1 μ kΩ kΩ 0.1 μF N.C. N.C. ...

Page 147

... PTA1 and PTA4 pins can be changed. Once out of reset, the MCU waits for the host to send eight security bytes (see security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to receive a command. Freescale Semiconductor μF 1 μ ...

Page 148

... MHz MHz clock at OSC1. 9.8304 2.4576 Provide external 9600 MHz MHz clock at OSC1. 3.2 MHz Internal clock is X 9600 (Trimmed) active OSC1 — — [13] TST ) then the chip will still be operating in lowered, the BIH and TST is applied to TST Freescale Semiconductor is ...

Page 149

... Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors. Modes Reset Vector High User $FFFE Monitor $FEFE Freescale Semiconductor NOTE , the MCU will come out of reset in user mode. Internal TST Figure 15-12. NOTE Table 15-2. Mode Difference Functions ...

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... Wait one bit time after each echo before sending the next byte. 150 BIT 6 BIT 2 BIT 3 BIT 4 BIT 5 Figure 15-13. Monitor Data Format MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO Figure 15-14. Break Transaction Table 15-1. NOTE MC68HC908QYA/QTA Family Data Sheet, Rev. 3 NEXT START STOP BIT 7 BIT BIT Freescale Semiconductor ...

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... Table 15-3. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A SENT TO MONITOR READ READ ECHO Freescale Semiconductor ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte ...

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... Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Command Sequence FROM HOST IREAD IREAD DATA Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO MC68HC908QYA/QTA Family Data Sheet, Rev. 3 DATA DATA DATA RETURN Freescale Semiconductor ...

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... CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value The high and low bytes of the program counter are at addresses and Figure 15-17. Stack Pointer at Monitor Mode Entry Freescale Semiconductor Command Sequence SP READSP ...

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... RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). 154 NOTE Figure 15-18. NOTE 4096 + 32 BUSCLKX4 CYCLES FROM HOST FROM MCU MC68HC908QYA/QTA Family Data Sheet, Rev Freescale Semiconductor ...

Page 155

... For proper operation recommended that V ≤ (V range unused inputs are connected to an appropriate logic voltage level (for example, either V Freescale Semiconductor NOTE (1) I PTA0— NOTE and V IN OUT ) ≤ ...

Page 156

... MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Temperature Value Unit – +125 °C – +105 – +85 2.7 to 5.5 V Value 105 142 76 90 133 User determined K/(T + 273°C) I 273° θ θ 150 With this value Freescale Semiconductor Code — Unit °C W/°C °C °C and ...

Page 157

... Guaranteed by design, not tested in production minimum V is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum reached measured 5 measured 5.0 V, Pulldown resistors only available when KBIx is enabled with KBIxPOL = Freescale Semiconductor Symbol OHT OHL HYS I ...

Page 158

... Figure 16-2. Typical 5-Volt Output Low Voltage 158 -5 -10 -15 -20 IOH (mA) versus Output High Current (25° IOL (mA) versus Output Low Current (25°C) MC68HC908QYA/QTA Family Data Sheet, Rev PTA 5V PTB -25 -30 5V PTA 5V PTB 25 30 Freescale Semiconductor ...

Page 159

... IRQ interrupt pulse period 4.5 to 5.5 Vdc Vdc noted. 2. Values are based on characterization results, not tested in production. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t RST IRQ Freescale Semiconductor (1) Symbol ( timing shown with respect to 20 ...

Page 160

... V V — 0 — 0. — — DD –2 — +2 –25 — +25 ±0.1 –1 +1 — — 8 750 — — 0.035 — — 2 4.0 — 2.40 2.55 2.70 2.475 2.625 2.775 — 75 — Freescale Semiconductor Unit μ V/ms V kΩ kΩ ...

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... Figure 16-4. Typical 3-Volt Output High Voltage 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-5. Typical 3-Volt Output Low Voltage Freescale Semiconductor -5 -10 -15 IOH (mA) versus Output High Current (25° IOL (mA) versus Output Low Current (25°C) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 ...

Page 162

... ILIL t ILIH Figure 16-6. RST and IRQ Timing MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Min Max (f ) — 4 Bus t 250 — cyc t 200 — 200 — ILIH (3) t — Note ILIL and 70 unless otherwise cyc Freescale Semiconductor Unit MHz cyc ...

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... The NRM must meet or exceed 10x the maximum ESR of the crystal or ceramic resonator for acceptable performance not use damping resistor when ECFS1:ECFS0 = 10. Consult crystal vendor data sheet. Freescale Semiconductor Symbol Min — ...

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... Electrical Specifications Figure 16-7. RC versus Frequency (5 Volts @ 25° Figure 16-8. RC versus Frequency (3 Volts @ 25°C) 164 ohms) ext ohms) ext MC68HC908QYA/QTA Family Data Sheet, Rev Freescale Semiconductor ...

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... ADC off, all modules enabled. All pins configured as inputs and tied DD to 0.2 V from rail. 5. Stop I measured with all pins configured as inputs and tied to 0.2 V from rail. On the 8-pin versions, port B is configured DD as inputs with pullups enabled. 6. For automotive applications only. Freescale Semiconductor Bus Voltage Frequency (MHz) 5.0 3.2 3.0 3 ...

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... MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Internal OSC (No A/D, ESCI, SPI) Internal OSC all Modules enabled External Reference No A/D External Reference All modules enabled 9 Internal OSC (No A/D, ESCI, SPI) Internal OSC all Modules enabled External OSC (No A/D) External OSC all Modules Enabled 5 Freescale Semiconductor ...

Page 167

... Long sample (ADLSMP = 1) Input voltage Input capacitance Input impedance Analog source impedance 10-bit mode Ideal resolution (1 LSB) 8-bit mode 10-bit mode Total unadjusted error 8-bit mode 10-bit mode Differential non-linearity 8-bit mode Freescale Semiconductor Conditions Symbol Min V 2.7 DD — ( — — (2) ...

Page 168

... Unit Comment Typ ±0.5 — LSB ±0.3 — ±0.5 — V LSB ADIN ±0.3 — ±0.5 — V LSB ADIN ±0.3 — ±0.5 — 8-bit mode is LSB not truncated ±0.5 — ±0.2 ±5 Pad leakage LSB ±0.1 ±1 1.245 1.32 V Freescale Semiconductor = (5) AS ...

Page 169

... Timer input clock pulse width 1. Values are based on characterization results, not tested in production. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t INPUT CAPTURE RISING EDGE INPUT CAPTURE FALLING EDGE INPUT CAPTURE BOTH EDGES TCLK Freescale Semiconductor t TLTL TLTL t TLTL t ...

Page 170

... HV NVS 5. Typical endurance was evaluated for this product family. For additional information on how Freescale Semiconductor defines Typical Endurance, please refer to Engineering Bulletin EB619. 6. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25• ...

Page 171

... MC908QY4A 1. See Table 17-3 for package information. Table 17-2. Automotive Device Numbering System Device Number S908QY2A S908QY4A 1. See Table 17-3 for package information. Freescale Semiconductor ADC FLASH Memory — 1536 bytes Yes 1536 bytes Yes 4096 bytes — 1536 bytes Yes ...

Page 172

... M = –40°C to +125°C RoHS COMPLIANCE DESIGNATOR (E = YES) PACKAGE DESIGNATOR DT = 16-PIN TSSOP DW = 16-PIN SOIC TEMPERATURE RANGE C = –40°C to +85° –40°C to +105° –40°C to +125°C MASK REVISION WAFER FAB Document No. 98ASB42420B 98ASH70107A 98ARL10557D 98ASB42431B 98ASB42567B 98ASH70247A Freescale Semiconductor ...

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... Monitor Mode. – A limitation of QY Classic debugging is that access to the ADC channels is limited because many of the QY Classic pins are multiplexed. Having extra ADC channels on the PTB pins resolves this limitation. Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev. 3 191 ...

Page 192

... ADC readings. (This bit location now used by ACLKEN was reserved — it always read and writes to that location had no affect.) 192 AIEN ADCO ADCH4 ADCH3 ADIV1 ADIV0 ADICLK MODE1 MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 ADCH2 ADCH1 ADCH0 Bit 0 0 AD9 AD8 Bit 0 MODE0 ADLSMP ACLKEN Freescale Semiconductor ...

Page 193

... The OSCOPT bits are no longer in the CONFIG2 register and now reside in the OSCSC register. Also, the ICFSx and ECFSx bits now reside in this register. The IFS bits are used to select different Internal Oscillator speeds. The ECFS bits are used to select the range of crystal that should be used to provide the reference clock. Freescale Semiconductor ...

Page 194

... The QYxA POR re-arm voltage will have a minimum specification of 0.7 V while the QYx Classic POR re-arm was 0.1 V. The higher POR re-arm voltage provides added protection against brown out conditions. 194 Unaffected MC68HC908QYA/QTA Family Data Sheet, Rev Bit 0 R OSCENINSTOP RSTEN Freescale Semiconductor ...

Page 195

... Separate routines will allow easy access to perform software SCI (Serial Communications Interface). For information on how to use on-chip FLASH programming routines refer to AN2635. • Finally, there is improved security and robustness. The latest Monitor ROM implements updated security checks to make the program memory more secure. Freescale Semiconductor ...

Page 196

... If so, since the OSCOPT bits have changed locations code will have to be updated to update these bits in their proper locations. 6. Does the code use the ADC? If so, because on QYxA the ADC clock is driven from 4XBUSCLK instead of BUSCLK changes to the ADC clock divider bits may be needed to maintain proper operation. 196 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 197

... QYxA. Emulation can be done using the EML08QCBLTYE. A.6 Differences in Packaging All QYxA packages will be lead free. All packages that the QYx classic supported will be supported by the QYxA. Freescale Semiconductor MC68HC908QYA/QTA Family Data Sheet, Rev. 3 197 ...

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... MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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