MC908QY4ACDWE Freescale Semiconductor, MC908QY4ACDWE Datasheet - Page 127

• Manufacturer Part Number: MC908QY4ACDWE
• Description: IC MCU 8BIT 4K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY4ACDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

14.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in
Output
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
Freescale Semiconductor
•
•
(IF AVAILABLE)
BUS CLOCK
When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
Compare. The pulses are unbuffered because changing the output compare value requires writing
INTERNAL
TCLK
TSTOP
TRST
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COUNTER
16-BIT LATCH
16-BIT LATCH
TMODH:TMODL
TCNTH:TCNTL
CHANNEL 0
CHANNEL 1
TCH0H:TCH0L
TCH1H:TCH1L
TCLK
PRESCALER
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
Figure 14-2. TIM Block Diagram
ELS0B
ELS1B
MS0A
MS1A
PS2
ELS0A
ELS1A
PRESCALER SELECT
PS1
CH0F
MS0B
CH1F
PS0
CH0MAX
CH1MAX
CH0IE
CH1IE
TOV0
TOV1
TOIE
TOF
INTERRUPT
INTERRUPT
INTERRUPT
Functional Description
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
PORT
PORT
14.3.3
TCH0
TCH1
127