R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 118

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
13.2.1
Table 13.7
NOTES:
Count Source
Count Operation
Division Ratio
Count Start Condition Write “1” (count starts) to the TZS bit in the TZMR register
Count Stop Condition Write “0” (count stops) to the TZS bit in the TZMR register
Interrupt Request
Generation Timing
TZOUT Pin Function Programmable I/O port
INT0 Pin Function
Read from Timer
Write to Timer
1. The IR bit in the TZIC register is set to “1” (interrupt requested) when writing to the TZPR or PREZ
Timer mode is mode to count a count source which is internally generated or Timer X underflow (see
Table 13.7 Specification of Timer Mode). The TZSC register is unused in timer mode. Figure 13.16
shows the TZMR and PUM Registers in Timer Mode.
<Conditions>
register while both of the following conditions are met.
When writing to the TZPR or PREZ register in the above state, disable an interrupt before writing.
•
•
Jan 19, 2006
Item
TZWC bit in TZMR register is set to “0” (write to reload register and counter simultaneously)
TZS bit in TZMR register is set to “1” (count starts)
Timer Mode
Specification of Timer Mode
(1)
f1, f2, f8, Timer X underflow
• Decrement
• When the timer underflows, it reloads the reload register contents before the
1/(n+1)(m+1) fi: Count source frequency
n: setting value in PREZ register, m: setting value in TZPR register
• When Timer Z underflows [Timer Z interrupt]
Programmable I/O port, or INT0 interrupt input
The count value can be read out by reading the TZPR and PREZ registers
• When writing to the TZPR and PREZ registers while the count stops, the value is
• When writing to the TZPR and PREZ registers during the count while the TZWC
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count continues (When Timer Z underflows, the contents of Timer Z primary
reload register is reloaded.)
written to both the reload register and counter.
bit is set to “0” (writing to the reload register and counter simultaneously), the
value is written to each reload register of the TZPR and PREZ registers at the
following count source input and the data is transferred to the counter at the
second count source input and the count re-starts at the third count source input.
When the TZWC bit is set to “1” (writing to only the reload register), the value is
written to each reload register of the TZPR and PREZ registers (the data is
transferred to the counter at the following reload).
Specification
13. Timers