R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 181

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
15.6
Figure 15.22
Table 15.4
1Tcyc=1/f1(s)
When setting the IIC in master mode.
Figure 15.22 shows the Timing of Bit Synchronous Circuit and Table 15.4 lists the Cycle between Setting
SCL Signal from “L” Output to High-Impedance and Monitoring SCL Signal.
•
•
When the SCL signal is driven to “L” by the slave device.
Since the “H” period may become shorter while the SCL signal is driven to “L” by the slave device
and the rising speed of the SCL signal is lowered by the load (load capacity and pull-up resistor) of
the SCL line, the SCL signal is monitored and the communication synchronizes per bit.
Bit Synchronous Circuit
Jan 19, 2006
CKS3
0
1
Monitoring SCL Signal
Timing of Bit Synchronous Circuit
Cycle between Setting SCL Signal from “L” Output to High-Impedance and
ICCR1 Register
Basis Clock of SCL
Page 166 of 254
Monitor Timing
Internal SCL
SCL
CKS2
0
1
0
1
VIH
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
Time for Monitoring SCL
15. I
2
C bus interface (IIC)