R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 79

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 11.5
Address Bus
11.1.6.4
CPU Clock
Data Bus
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt
routine execution.
When an interrupt request is generated while an instruction is executed, the CPU determines its
interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from
the following cycle. However, in regards to the SMOVB, SMOVF, SSTR or RMPA instruction, if an
interrupt request is generated while executing the instruction, the microcomputer suspends the
instruction to start the interrupt sequence. The interrupt sequence is performed as follows. Figure
11.5 shows the Time Required for Executing Interrupt Sequence.
After the interrupt sequence is completed, the instructions are executed from the starting address of
the interrupt routine.
NOTES:
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
WR
RD
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU
(3) The I, D and U flags in the FLG register are set as follows:
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
Jan 19, 2006
1. This register cannot be used by user.
the address 00000h. The IR bit for the corresponding interrupt is set to “0” (interrupt not
requested).
internal temporary register
The I flag is set to “0” (disables interrupts).
The D flag is set to “0” (disables single-step interrupt).
The U flag is set to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt numbers
32 to 63 is executed.
1
Interrupt Sequence
Time Required for Executing Interrupt Sequence
2
Address
0000h
information
Interrupt
3
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4
5
Indeterminate
Indeterminate
Indeterminate
6
(1)
.
7
8
SP-2 SP-1
9
(1)
contents
SP-2
is saved to the stack.
10
contents
SP-1
SP-4
11
contents
SP-4
12
SP-3
contents
SP-3
13
VEC
14
contents
VEC
15
VEC+1
contents
VEC+1
16
17
VEC+2
contents
VEC+2
18
19
11. Interrupt
PC
20