R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 145

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
14.1
Table 14.1
NOTES:
Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
The clock synchronous serial I/O mode is mode to transmit and receive data using a transfer clock. Table
14.1 lists the Specification of Clock Synchronous Serial I/O Mode. Table 14.2 lists the Registers to Be
Used and Settings in Clock Synchronous serial I/O Mode.
1. When an external clock is selected, meet the conditions while the CKPOL bit in the U0C0 register is
2. If an overrun error occurs, the value of the U0RB register will be indeterminate. The IR bit in the
set to “0” (transmit data output at the falling edge and the receive data input at the rising edge of the
transfer clock), the external clock is held “H”; if the CKPOL bit in the U0C0 register is set to “1”
(transmit data output at the rising edge and the receive data input at the falling edge of the transfer
clock), the external clock is held “L”.
S0RIC register remains unchanged.
Clock Synchronous Serial I/O Mode
Jan 19, 2006
Item
Specification of Clock Synchronous Serial I/O Mode
Page 130 of 254
• Transfer data length: 8 bits
• The CKDIR bit in the U0MR register is set to “0” (internal clock): fi/(2(n+1))
• The CKDIR bit is set to “1” (external clock): input from the CLK0 pin
• Before transmit starts, the following requirements are required
• Before receive starts, the following requirements are required
• When transmit, one of the following conditions can be selected
• When receive
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
fi=f1, f8, f32 n=setting value in U0BRG register: 00h to FFh
- The TE bit in the U0C1 register is set to “1” (transmit enabled)
- The TI bit in the U0C1 register is set to “0” (data in the U0TB register)
- The RE bit in the U0C1 register is set to “1” (receive enabled)
- The TE bit in the U0C1 register is set to “1” (transmit enabled)
- The TI bit in the U0C1 register is set to “0” (data in the U0TB register)
- The U0IRS bit is set to “0” (transmit buffer empty):
- The U0IRS bit is set to “1” (transmit completes):
When transferring data from the UART0 receive register to the U0RB
register (when receive completes)
This error occurs if serial interface starts receiving the following data before
reading the U0RB register and receives the 7th bit of the following data
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock
Whether transmitting or receiving data beginning with the bit 0 or beginning
with the bit 7 can be selected
Receive is enabled immediately by reading the U0RB register
when transferring data from the U0TB register to UART0 transmit register
(when transmit starts)
when completing transmit data from UARTi transmit register
(2)
Specification
14. Serial Interface
(1)
(1)