R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 182

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
15.7
Figure 15.23
Figure 15.23 to Figure 15.26 show the Examples of Register Setting When Using IIC.
Example of Register Setting
Jan 19, 2006
Example of Register Setting in Master Transmit Mode
ICCR1 Register
ICCR2 Register
ICSR Register
ICSR Register
ICCR2 Register
ICCR1 Register
ICSR Register
Read STOP bit in ICSR register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Write transmit data to ICDRT register
Read ACKBR bit in ICIER register
Read BBSY bit in ICCR2 register
Read TEND bit in ICSR register
Read TDRE bit in ICSR register
Read TEND bit in ICSR register
No
No
Page 167 of 254
No
No
No
No
Initial Setting
ACKBR=0 ?
Yes
Last Byte ?
BBSY=0 ?
TEND=1 ?
TDRE=1 ?
TEND=1 ?
Transmit
STOP=1 ?
BBSY Bit ← 1
Mode ?
BBSY Bit ← 0
TDRE Bit ← 0
MST Bit ← 1
MST Bit ← 0
Start
TEND Bit ← 0
TRS Bit ← 1
SCP Bit ← 0
SCP Bit ← 0
TRS Bit ← 0
End
STOP Bit ← 0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Master Receive
Mode
(1) Judge the state of the SCL and SDA lines
(2) Set to master transmit mode
(3) Generate the start condition
(4) Set the transmit data of the 1st byte
(5) Wait for 1 byte to be transmitted
(6) Judge the ACKBR bit from the specified slave device
(7) Set the transmit data after 2nd byte (except the last byte)
(8) Wait the ICRDT register is empty
(9) Set the transmit data of the last byte
(10) Wait for the transmit end of the last byte
(11) Set the TEND bit to “0”
(12) Set the STOP bit to “0”
(13) Generate the stop condition
(14) Wait the stop condition is generated
(15) Set to slave receive mode
(slave address + R/W)
Set the TDRE bit to “0”
15. I
2
C bus interface (IIC)