R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 143

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 14.4
UART0 Transmit / Receive Mode Register
UART0 Transmit / Receive Control Register 0
b7 b6 b5 b4
NOTES :
b7 b6 b5 b4
NOTES :
0
1.
1.
Set the PD1_6 bit in the PD1 register to “0” (input).
If the BRG count source is sw itched, set the U0BRG register again.
Jan 19, 2006
b3 b2 b1 b0
b3 b2
0
U0MR and U0C0 Registers
b1 b0
Bit Symbol
Bit Symbol
Symbol
UFORM
Symbol
CKPOL
CKDIR
TXEPT
U0MR
SMD0
SMD1
SMD2
PRYE
STPS
U0C0
CLK0
CLK1
PRY
NCH
(b7)
(b2)
(b4)
Page 128 of 254
—
—
—
Serial Interface Mode Select Bit
Internal / External Clock Select
Bit
Stop Bit Length Select Bit
Odd / Even Parity Select Bit
Parity Enable Bit
Reserved Bit
BRG Count Source Select
Bit
Reserved Bit
Transmit Register Empty
Flag
Nothing is assigned. When w rite, set to “0”.
When read, its content is “0”.
Data Output Select Bit
CLK Polarity Select Bit
Transfer Format Select Bit 0 : LSB first
(1)
Address
Bit Name
00A4h
Address
Bit Name
00A0h
b1 b0
0 0 : Selects f1
0 1 : Selects f8
1 0 : Selects f32
1 1 : Do not set
Set to “0”
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
0 : TXD0 pin is a pin of CMOS output
1 : TXD0 pin is a pin of N-channel open drain output
0 : Transmit data is output at falling edge of transfer
1 : Transmit data is output at rising edge of transfer
1 : MSB first
clock and receive data is input at rising edge
clock and receive data is input at falling edge
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set
0 : Internal clock
1 : External clock
0 : 1 Stop Bit
1 : 2 Stop Bits
Enables w hen PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
Set to “0”
After Reset
Function
(1)
After Reset
08h
Function
00h
14. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
—