R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 180
R5F21162SP#U0
Manufacturer Part Number
R5F21162SP#U0
Description
IC R8C MCU FLASH 8K 20SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/16r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21173DSPU0.pdf
(40 pages)
3.R5F21173DSPU0.pdf
(281 pages)
Specifications of R5F21162SP#U0
Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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- Download datasheet (4Mb)
R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
15.5
Figure 15.21
The state of the SCL and SDA pins are routed through the noise rejection circuit before being latched
internally. Figure 15.21 shows the Block Diagram of Noise Rejection Circuit.
The noise rejection circuit consists of two cascaded latch and match detector circuits. When the SCL
pin input signal (or SDA pin input signal) is sampled on f1 and 2 latch outputs match, the level is
passed forward to the next circuit. When they do not match, the former value is retained.
f1 (Sampling Clock)
Noise Rejection Circuit
Jan 19, 2006
SCL or SDA
Input Signal
Block Diagram of Noise Rejection Circuit
Page 165 of 254
f1 (Sampling Clock)
Period of f1
D
Latch
C
Q
D
Latch
C
Q
Detection
Circuit
Match
15. I
2
Internal SCL
or SDA Signal
C bus interface (IIC)
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