R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 204
R5F21334CNFP#U0
Manufacturer Part Number
R5F21334CNFP#U0
Description
MCU 1KB FLASH 16K ROM 32-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/33Cr
Datasheet
1.R5F21331CNFPU0.pdf
(622 pages)
Specifications of R5F21334CNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21334CNFP#U0R5F21334CNFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 174 of 589
14.3.2
Table 14.2
Notes:
Count source
Count operation
Period
Watchdog timer
initialization conditions
Count start conditions
Count stop condition
Operations at underflow
The count source for the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 14.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Disabled).
1. The watchdog timer is initialized when 00h and then FFh is written to the WDTR register. The
2. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh
3. Write the WDTR register during the count operation of the watchdog timer.
prescaler is initialized after a reset. This may cause some errors due to the prescaler during the
watchdog timer period.
with a flash programmer.
Count Source Protection Mode Disabled
Item
Watchdog Timer Specifications (Count Source Protection Mode Disabled)
CPU clock
Decrement
Division ratio of prescaler (n) × count value of watchdog timer (m)
n: 16 or 128 (selected by the WDTC7 bit in the WDTC register), or
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Example:
The period is approximately 13.1 ms when:
- The CPU clock frequency is set to 20 MHz.
- The prescaler is divided by 16.
- Bits WDTUFS1 to WDTUFS0 are set to 11b (3FFFh).
• Reset
• Write 00h and then FFh to the WDTR register.
• Underflow
The operation of the watchdog timer after a reset is selected by
the WDTON bit
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset).
• When the WDTON bit is set to 0 (watchdog timer starts automatically after
Stop mode, wait mode (Count resumes from the retained value after exiting.)
• When the PM12 bit in the PM1 register is set to 0.
• When the PM12 bit in the PM1 register is set to 1.
The watchdog timer and prescaler are stopped after a reset and
start counting when the WDTS register is written to.
reset).
The watchdog timer and prescaler start counting automatically after a reset.
Watchdog timer interrupt
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset )
2 when selecting the low-speed clock (CM07 bit in CM0 register = 1)
(2)
in the OFS register (address 0FFFFh).
CPU clock
Specification
(3)
14. Watchdog Timer
(1)
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