M30840SGP#U5 Renesas Electronics America, M30840SGP#U5 Datasheet - Page 117

• Manufacturer Part Number: M30840SGP#U5
• Description: IC M32C/84 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30840SGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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Figure 9.12 Procedure to Use PLL Clock as CPU Clock Source
Table 9.3 Bit Settings to Use PLL Clock as CPU Clock Source
0
C
9.1.4 PLL Clock
1
9
0 .
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B
1
The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be
used as clock source for the CPU clock and peripheral function clock.
The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL
frequency synthesizer starts operating. Wait
The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or
divided-by-3. When the PLL clock is used as a clock source for the CPU clock or peripheral function
clock, set each bit as is shown in Table 9.3. Figure 9.12 shows the procedure to use the PLL clock as the
CPU clock source.
To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), set the PLC07 bit
in the PLC0 register to "0" (PLL off) and then enter wait or stop mode.
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Use PLL clock as CPU clock source
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Set the PLC0 and the PLC1 registers
0
(PLL clock as CPU clock source)
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Set the PLC07 bit to "1"
(Set the PLC07 bit to "0")
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Set the CM17 bit to "1"
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Wait tsu
(PLL on)
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(PLL)
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t i
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(PLL)
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ms for the PLL clock to stabilize.
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PLC07 bit : Bit in the PLC0 Register
CM17 bit : Bit in the CM1 Register
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9. Clock Generation Circuit