M30840SGP#U5 Renesas Electronics America, M30840SGP#U5 Datasheet - Page 245

• Manufacturer Part Number: M30840SGP#U5
• Description: IC M32C/84 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30840SGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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Figure 17.21 Start Condition or Stop Condition Detecting
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17.3.1 Detecting Start Condition and Stop Condition
17.3.2 Start Condition or Stop Condition Output
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The microcomputer detects either a start condition or stop condition. The start condition detect interrupt
is generated when the SCLi (i=0 to 4) pin level is held high ("H") and the SDAi pin level changes "H" to low
("L"). The stop condition detect interrupt is generated when the SCLi pin level is held "H" and the SDAi pin
level changes "L" to "H". The start condition detect interrupt shares interrupt control registers and vectors
with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which interrupt is
requested.
The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1"
(start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1"
(start). The stop condition is generated the STPREQ bit in the UiSMR4 is set to "1" (start).
The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4
register is set to "1" (start or stop condition generating circuit selected). The restart condition output is
provided when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition output is provided
when the STPREQ bit and the STSPSEL bit are set to "1".
When the start condition, stop condition or restart condition is output, do not generate an interrupt be-
tween the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set
the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the
STSPSEL bit is set to "1".
Table 17.18 lists function of the STSPSEL bit. Figure 17.22 shows functions of the STSPSEL bit.
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(Start condition)
(Stop condition)
i=0 to 4
NOTES:
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1. These cycles are main clock generation frequency cycles (X
3 to 6 cycles < setup time
3 to 6 cycles < hold time
SDAi
SDAi
SCLi
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f o
4
4
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(1)
(1)
Setup time
Hold time
17. Serial I/O (Special Function)
IN
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