M30840SGP#U5 Renesas Electronics America, M30840SGP#U5 Datasheet - Page 231

• Manufacturer Part Number: M30840SGP#U5
• Description: IC M32C/84 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30840SGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 17.13 Serial Data Logic Inverse
0
C
17.1.3 Continuous Receive Mode
17.1.4 Serial Data Logic Inverse
1
9
8 /
0 .
B
When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set
to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set
dummy data in the UiTB register by program.
When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB
register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB
register. Figure 17.13 shows a switching example of the serial data logic.
0
1
4
0
G
3
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
3
0
2
5
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
Transfer clock
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed)
Transfer clock
NOTES:
C
8 /
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on
(no inverse)
Page 208
the falling edge) and the UFORM bit in the UiC register is set to "0" (LSB first).
, 4
(inverse)
M
TxD
TxD
3
2
i
i
C
"H"
"H"
"H"
"H"
"L"
8 /
"L"
"L"
"L"
f o
4
4
) T
9
5
D
D
0
0
D
D
1
1
D
D
2
2
D
D
3
3
D
D
4
4
17. Serial I/O (Clock Synchronous Serial I/O)
D
D
5
5
D
D
6
6
D
D
7
7