M30840SGP#U5 Renesas Electronics America, M30840SGP#U5 Datasheet - Page 97

• Manufacturer Part Number: M30840SGP#U5
• Description: IC M32C/84 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30840SGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
NOTES:
Figure 8.10 ALE Signal and Address/Data Bus
Table 8.6 Microcomputer States in Wait State
0
R
n I
C
O
C
8.2.5 ALE Signal
1
8.2.6 RDY Signal
9
D
, S
1. The RDY signal cannot be accepted immediately before software wait states are inserted.
0 .
8 /
s
e t
D
B
The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the
ALE signal. The PM15 and PM14 bits in the PM1 register determine the output pin for the ALE signal.
The ALE signal is output to internal space and external space.
The RDY signal facilitates access to external devices requiring longer access time. When a low-level ("L")
signal is applied to the RDY pin on the falling edge of the last BCLK of the bus cycle, wait states are
inserted into the bus cycle. When a high-level ("H") signal is applied to the RDY pin on the falling edge of
BCLK, the bus cycle starts running again.
Table 8.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure
8.11 shows an example of the RD signal that is extended by the RDY signal.
i c
0
0
n r
1
S
4
(1) 8-Bit Data Bus
/A
a l l
A
0
g i
l a
L
3
G
A
J
0
o i t
n
A
E
6
u
16
A
A
A
A
_______
o r
to D
P
, l a
8
0 -
. l
20
21
22
23
n
_______
S
r e
________
u
to A
to A
0
1
g i
/CS3
/CS2
/CS1
/CS0
W
p
p i
, 7
0
ALE
7
n
/A
1
h
R
(
15
19
, l a
2
M
r e
7
0
S
3
l a
0
H
NOTES:
g i
5
2
L
n
C
C
1. D
2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port.
D
, l a
r i
8 /
, A
u c
I
Page 74
Address
, 4
e t
A
0
P
s t i
/A
d
m
o r
d
M
0
e r
g
to D
3
Address or CS
________
a r
s s
2
C
m
Address
Address
7
B
f o
8 /
/A
m
u
a
7
4
, s
4
b
) T
are placed in high-impedance states when read.
9
_____
e l
D
5
a
(2)
I
a t
O /
Data
B
P
u
r o
(1)
, s
s t
O
M
s
O
g i
n
a
n
(1)
n
n i
________
l a
i a t
w
s n
D
s a
0
h t
/A
r
c e
e
0
to D
A
a s
i e
(2) 16-Bit Data Bus
16
A
A
A
A
e v
m
20
21
22
23
15
to A
e
d
/CS3
/CS2
/CS1
/CS0
ALE
/A
s
S
a t
19
15
a t
________
e t
e t
s a
w
h
Address
e
n
________
R
Address or CS
D
Y
Address
(2)
Data
(1)
8. Bus