M30840SGP#U5 Renesas Electronics America, M30840SGP#U5 Datasheet - Page 376

IC M32C/84 MCU ROMLESS 100LQFP

M30840SGP#U5

Manufacturer Part Number
M30840SGP#U5
Description
IC M32C/84 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M30840SGP#U5

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30840SGP#U5M30840SGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30840SGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
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R
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E
3
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J
2
0
C
1
9
8 /
0 .
B
0
1
4
The C0GMRk, C0LMARk and C0LMBRk registers are used for acceptance filtering.
The users can select and receive user-desired messages.
The C0GMRk register determines whether IDs in the message slots 0 to 13 are verified. The
C0LMARk register determines whether ID in the message slot 14 is verified. The C0LMBRk register
determines whether ID in the message slot 15 is verified.
Figure 23.27 shows each mask register and corresponding message slot. Figure 23.28 shows the
acceptance filtering.
0
G
3
J
NOTES:
6
u
• When bits in these registers are set to "0", each standard ID0 and standard ID1 bits (ID bit) and
• When bits in these registers are set to "1", corresponding ID bits are compared with received IDs
o r
0 -
. l
extended ID0 to extended ID2 bits in the CAN0 message slots j (j=0 to 15) corresponding to the
bits in the above registers, is masked while acceptance filtering. (The corresponding bits are as-
sumed to have matching IDs.)
while acceptance filtering. If the received ID matches the ID in the message slot j, the received
data having the matched ID is stored into that message slot.
u
1. Change the C0GMRk register setting only when the message slots 0 to 13 have no receive request.
2. Change the C0LMARk register setting only when the message slot 14 has no receive request.
3. Change the C0LMBRk register setting only when the message slot 15 has no receive request.
4. More than two message slots are able to store a receive message ID, the ID is stored into the
0
1
p
, 7
0
message slot, having the smallest slot number.
1
(
2
M
0
3
0
2
5
C
8 /
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23. CAN Module

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