M30840SGP#U5 Renesas Electronics America, M30840SGP#U5 Datasheet - Page 374

• Manufacturer Part Number: M30840SGP#U5
• Description: IC M32C/84 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30840SGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 23.25 C0GMR3, C0LMAR3 and C0LMBR3 Registers
0
C
1
9
8 /
0 .
B
0
1
4
0
G
3
J
6
u
o r
0 -
. l
u
0
1
CAN0 Global Mask Register Extended ID1
CAN0 Local Mask Register A Extended ID1
CAN0 Local Mask Register B Extended ID1
b7
p
, 7
0
NOTES:
1
(
2
b6
M
0
1. The C0GMR3, C0LMAR3 and C0LMBR3 registers can be accessed only when the BANKSEL bit in
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after
3. The C0LMAR3 register shares the same address with the C0MCTL3 register.
4. The C0LMBR3 register shares the same address with the C0MCTL11 register..
3
0
b5
2
5
the C0CTLR1 register is set to "1" (mask register selected).
reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0".
C
b4
8 /
Page 351
, 4
b3
M
b2
3
2
b1
C
8 /
f o
b0
4
4
) T
9
EID10M
EID11M
EID12M
EID13M
Symbol
EID6M
EID7M
EID8M
EID9M
5
Bit
Symbol
C0GMR3
C0LMAR3
C0LMBR3
Extended ID6
Extended ID7
Extended ID8
Extended ID9
Extended ID10
Extended ID11
Extended ID12
Extended ID13
Bit Name
Address
022B
0233
023B
16
16
16 (4)
0: No ID is verified
1: ID is verified
(1)
(3)
(1)
(1)
Function
After Reset
00
00
00
16
16
16
(2)
23. CAN Module
RW
RW
RW
RW
RW
RW
RW
RW
RW