DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 394

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
13.4.4
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described below. When the operating mode, or transfer format, is changed for
example, the TE and RE bits must be cleared to 0 before making the change using the following
procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit
to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of
RDR. When the external clock is used in asynchronous mode, the clock must be supplied even
during initialization.
Rev. 5.00 Sep. 01, 2009 Page 342 of 656
REJ09B0071-0500
SCI Initialization (Asynchronous Mode)
SCR to 1, and set RIE, TIE, TEIE,
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
SMR, SCMR, and SEMR_0
Set data transfer format in
<Initialization completion>
Set TE and RE bits * in
1-bit interval elapsed?
Set value in BRR
Start initialization
(TE, RE bits 0)
and MPIE bits
Figure 13.8 Sample SCI Initialization Flowchart
Yes
Wait
No
[1]
[2]
[3]
[4]
Note: * Perform this set operation with the
[1] Set the clock selection in SCR.
[2] Set the data transfer format in
[3] Write a value corresponding to the
[4] Wait at least one bit interval, then
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
SMR, SCMR and SEMR_0.
bit rate to BRR. Not necessary if
an external clock or an average
transfer rate clock by bits AC2 to
ACS0 in SEMR_0 is used.
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
RxD pin in the 1 state. If the RE bit is
set to 1 with the RxD pin in the 0
state, it may be misinterpreted as a
start bit.