DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 630

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 24 List of Registers
Rev. 5.00 Sep. 01, 2009 Page 578 of 656
REJ09B0071-0500
Register Name
Port 1 data register
Port 3 data register
Port 7 data register
Port F data register
Timer control register_0 *
Timer mode register_0 *
Timer I/O control register H_0 *
Timer I/O control register L_0 *
Timer interrupt enable
register_0 *
Timer status register_0 *
Timer counter_0 *
Timer general register A_0 *
Timer general register B_0 *
Timer general register C_0 *
Timer general register D_0 *
Timer control register_1
Timer mode register_1
Timer I/O control register_1
Timer interrupt enable
register_1
Timer status register_1
Timer counter_1
Timer general register A_1
Timer general register B_1
Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable
register_2
Timer status register_2
4
4
4
4
4
4
4
4
4
4
4
Abbreviation Bit No. Address *
P1DR
P3DR
P7DR
PFDR
TCR_0
TMDR_0
TIORH_0
TIORL_0
TIER_0
TSR_0
TCNT_0
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TCR_1
TMDR_1
TIOR_1
TIER_1
TSR_1
TCNT_1
TGRA_1
TCR_2
TMDR_2
TIOR_2
TIER_2
TSR_2
TGRB_1
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
8
8
8
8
8
16
16
16
8
8
8
8
8
H'FF00
H'FF02
H'FF06
H'FF0E
H'FF10
H'FF11
H'FF12
H'FF13
H'FF14
H'FF15
H'FF16
H'FF18
H'FF1A
H'FF1C
H'FF1E
H'FF20
H'FF21
H'FF22
H'FF24
H'FF25
H'FF26
H'FF28
H'FF2A
H'FF30
H'FF31
H'FF32
H'FF34
H'FF35
1
TPU_0
TPU_0
Module
PORT
PORT
PORT
PORT
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
Data
Width
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
8
8
8
8
8
16
16
16
8
8
8
8
8
Access
State
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2