DF2265TE13V Renesas Electronics America, DF2265TE13V Datasheet - Page 471

• Manufacturer Part Number: DF2265TE13V
• Description: IC H8S/2265 MCU FLASH 100TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2265TE13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The reception procedure and operations in slave receive mode are described below.
1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
2. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
3. When the slave address matches in the first frame following the start condition, the device
4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Read the
Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is
changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in
ICCR is cleared to 0.
according to the operating mode.
to 1.
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1, the slave device drives SCL low from the fall of the receive clock until data
is read into ICDR.
IRDR flag and clear the IRIC flag to 0 consecutively, with no interrupt processing occurring
between them. If the time needed to transmit one byte of data elapses before the IRIC flag is
cleared, it will not be possible to determine when the transfer has completed.
Section 14 I
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Rev. 5.00 Sep. 01, 2009 Page 419 of 656
REJ09B0071-0500