UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 13
UPD70F3735GK-GAK-AX
Manufacturer Part Number
UPD70F3735GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3735GC-GAD-AX.pdf
(835 pages)
Specifications of UPD70F3735GK-GAK-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3735GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 591
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 614
17.14 Communication Reservation............................................................................................... 570
17.15 Cautions ................................................................................................................................ 575
17.16 Communication Operations ................................................................................................ 576
17.17 Timing of Data Communication .......................................................................................... 584
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10 DMA Abort Factors............................................................................................................... 604
18.11 End of DMA Transfer............................................................................................................ 604
18.12 Operation Timing .................................................................................................................. 604
18.13 Cautions ................................................................................................................................ 609
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................570
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................574
17.16.1 Master operation in single master system................................................................................577
17.16.2 Master operation in multimaster system ..................................................................................577
17.16.3 Slave operation........................................................................................................................581
Features................................................................................................................................. 591
Configuration ........................................................................................................................ 592
Registers ............................................................................................................................... 593
Transfer Targets ................................................................................................................... 600
Transfer Modes ..................................................................................................................... 600
Transfer Types ...................................................................................................................... 601
DMA Channel Priorities........................................................................................................ 602
Time Related to DMA Transfer ............................................................................................ 602
DMA Transfer Start Factors................................................................................................. 603
Features................................................................................................................................. 614
Non-Maskable Interrupts ..................................................................................................... 618
19.2.1
19.2.2
19.2.3
Maskable Interrupts.............................................................................................................. 623
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
Software Exception .............................................................................................................. 636
19.4.1
19.4.2
19.4.3
Exception Trap...................................................................................................................... 639
19.5.1
19.5.2
External Interrupt Request Input Pins (NMI and INTP0 to INTP7) ................................... 643
19.6.1
19.6.2
Interrupt Acknowledge Time of CPU .................................................................................. 648
Periods in Which Interrupts Are Not Acknowledged by CPU .......................................... 649
Operation .................................................................................................................................620
Restore ....................................................................................................................................621
NP flag .....................................................................................................................................622
Operation .................................................................................................................................623
Restore ....................................................................................................................................625
Priorities of maskable interrupts...............................................................................................626
Interrupt control register (xxICn) ..............................................................................................630
Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................632
In-service priority register (ISPR).............................................................................................634
ID flag ......................................................................................................................................635
Watchdog timer mode register 2 (WDTM2) .............................................................................635
Operation .................................................................................................................................636
Restore ....................................................................................................................................637
EP flag .....................................................................................................................................638
Illegal opcode...........................................................................................................................639
Debug trap ...............................................................................................................................641
Noise elimination .....................................................................................................................643
Edge detection.........................................................................................................................643
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