UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 758

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
29.2 Debugging Without Using DCU
and TXDA0) or pins for CSIB0 (SIB0, SOB0, SCKB0, and HS (PCM0)) as debug interfaces, without using the DCU.
29.2.1 Circuit connection examples
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
The following describes how to implement an on-chip debug function using MINICUBE2 with pins for UARTA0 (RXDA0
Notes 1. Connect TXDA0/SOB0 (transmit side) of the V850ES/JF3-L to RXD/SI (receive side) of the target
Remark Refer to Table 29-3 for pins used when UARTA0 or CSIB0 is used for communication interface.
Figure 29-3. Circuit Connection Example When UARTA0/CSIB0 Is Used for Communication Interface
3. The V850ES/JF3-L-side pin connected to this pin (FLMD0, FLMD1) can be used as an alternate-
4. This connection is designed assuming that the RESET signal is output from the N-ch open-drain
2. This pin may be used to supply a clock from MINICUBE2 during flash memory programming. For
5. The circuit enclosed by a dashed line is designed for flash self programming, which controls the
connector, and TXD/SO (transmit side) of the target connector to RXDA0/SIB0 (receive side) of the
V850ES/JF3-L.
details, refer to CHAPTER 28 FLASH MEMORY.
function pin other than while the memory is rewritten during a break in debugging, because this pin is
in a Hi-Z state.
buffer (output resistance: 100 Ω or less).
FLMD0 pin via ports.
programming is not performed, a pull-down resistance for the FLMD0 pin can be within 1 to 10 kΩ.
RESET_IN
RESET_OUT
QB-MINI2
TXD/SO
RXD/SI
FLMD1
FLMD0
CLK
GND
VDD
SCK
Note 1
Note 1
Note 2
Note 3
Note 3
Note 4
HS
V
Use the port for inputting or outputting the high level.
DD
10 kΩ
1 to 10 kΩ
1 to 10 kΩ
1 to 10 kΩ
V
V
DD
DD
1 kΩ
V
DD
3 to 10 kΩ
CHAPTER 29 ON-CHIP DEBUG FUNCTION
1 to 10 kΩ
10 kΩ
RESET signal
V
DD
100 Ω
V
RESET
TXDA0/SOB0
V
RXDA0/SIB0
SCKB0
HS (PCM0)
FLMD1
FLMD0
Port X
DD
SS
V850ES/JF3-L
Reset circuit
When flash self
Note 5
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