UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 686

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
21.6.2 Releasing STOP mode/low-voltage STOP mode
INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt
request signal from the peripheral functions operable in the STOP mode and low-voltage STOP mode, or reset signal
(reset by RESET pin input, WDT2RES signal, or low-voltage detector (LVI)).
oscillation stabilization time has been secured.
mode.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Non-maskable interrupt request
signal
Maskable interrupt request signal
The STOP mode and low-voltage STOP mode are released by a non-maskable interrupt request signal (NMI pin input,
After the STOP mode or low-voltage STOP mode has been released, the normal operation mode is restored after the
For re-setting after the low-voltage STOP mode is released, see 21.6.3 Re-setting after release of low-voltage STOP
(1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request
(2) Releasing STOP mode by reset
signal
The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the STOP mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is
The same operation as the normal reset operation is performed.
Caution The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits
Release Source
issued, the STOP mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
issued (including a non-maskable interrupt request signal), the STOP mode is released and that interrupt
request signal is acknowledged.
to 1 becomes invalid and STOP mode is not released.
Table 21-10. Operation After Releasing STOP Mode by Interrupt Request Signal
Execution branches to the handler address after securing the oscillation stabilization time.
Execution branches to the handler address
or the next instruction is executed after
securing the oscillation stabilization time.
Interrupt Enabled (EI) Status
The next instruction is executed after
securing the oscillation stabilization time.
CHAPTER 21 STANDBY FUNCTION
Interrupt Disabled (DI) Status
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