UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 697

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
21.8.2 Releasing sub-IDLE mode/low-voltage sub-IDLE mode
INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt
request signal from the peripheral functions operable in the sub-IDLE mode/low-voltage sub-IDLE mode, or reset signal
(reset by RESET pin input, WDT2RES signal, low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the
operating status it was in before the sub-IDLE mode was set. It returns to the stop status in the low-voltage sub-IDLE
mode.
mode is set.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Non-maskable interrupt request
signal
Maskable interrupt request signal
The sub-IDLE mode/low-voltage sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input,
When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set.
When the low-voltage sub-IDLE mode is released by an interrupt request signal, the low-voltage subclock operation
For releasing low-voltage subclock operation mode, see 21.7.3 Releasing low-voltage subclock operation mode.
(1) Releasing sub-IDLE mode/low-voltage sub-IDLE by non-maskable interrupt request signal or unmasked
(2) Releasing sub-IDLE mode/low-voltage sub-IDLE by reset
maskable interrupt request signal
The sub-IDLE mode/low-voltage sub-IDLE is released by a non-maskable interrupt request signal or an unmasked
maskable interrupt request signal, regardless of the priority of the interrupt request signal.
If the sub-IDLE mode/low-voltage sub-IDLE is set in an interrupt servicing routine, however, an interrupt request
signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is
Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and
The same operation as the normal reset operation is performed.
Release Source
issued, the sub-IDLE mode/low-voltage sub-IDLE is released, but that interrupt request signal is not
acknowledged. The interrupt request signal itself is retained.
issued (including a non-maskable interrupt request signal), the sub-IDLE mode/low-voltage sub-IDLE mode is
released and that interrupt request signal is acknowledged.
Table 21-15. Operation After Releasing Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode
2. When the sub-IDLE mode/low-voltage sub-IDLE mode is released, 12 cycles of the subclock
PSC.INTM bits to 1 becomes invalid and sub-IDLE mode/low-voltage sub-IDLE mode is not
released.
(about 366
mode/low-voltage sub-IDLE is generated to when the mode is released.
μ
Execution branches to the handler address.
Execution branches to the handler address
or the next instruction is executed.
s) elapse from when the interrupt request signal that releases the sub-IDLE
Interrupt Enabled (EI) Status
by Interrupt Request Signal
The next instruction is executed.
CHAPTER 21 STANDBY FUNCTION
Interrupt Disabled (DI) Status
Page 681 of 816