UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 678
UPD70F3735GK-GAK-AX
Manufacturer Part Number
UPD70F3735GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3735GC-GAD-AX.pdf
(835 pages)
Specifications of UPD70F3735GK-GAK-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3735GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JF3-L
Note To realize low power consumption, stop the A/D converter and D/A converter before shifting to the IDLE1 mode.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Non-maskable interrupt request
signal
Maskable interrupt request signal
Item
LVI
Main clock oscillator
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP2, TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
(2) Releasing IDLE1 mode by reset
The same operation as the normal reset operation is performed.
Release Source
Setting of IDLE1 Mode
Table 21-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal
CSIB0 to CSIB2
I
UARTA0 to UARTA2
2
C00, I
2
C01
Execution branches to the handler address.
Execution branches to the handler address
or the next instruction is executed.
Table 21-5. Operating Status in IDLE1 Mode
Operable
Oscillaties
Oscillation enabled
Operable
Stops operation
Stops operation
Stops operation (but standby mode release enabled)
Stops operation
Stops operation
Operable when f
count clock
Operable when f
selected as the count clock
Operable when f
count clock
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 2)
Stops operation
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
Holds operation (conversion result held)
Holds operation (output held
Stops operation (output held)
Operable
Stops operation
See 2.2 Pin States.
Retains status before IDLE1 mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the IDLE1 mode was set.
Interrupt Enabled (EI) Status
When Subclock Is Not Used
R
X
R
/8 is selected as the
(divided BRG) is
is selected as the
−
Note
)
Operating Status
Note
The next instruction is executed.
CHAPTER 21 STANDBY FUNCTION
Oscillaties
Operable when f
the count clock
Operable
Operable when f
the count clock
Interrupt Disabled (DI) Status
When Subclock Is Used
R
R
/8 or f
or f
XT
XT
is selected as
is selected as
Page 662 of 816
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