UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 655

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UPD70F3735GK-GAK-AX

Manufacturer Part Number
UPD70F3735GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GK-GAK-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
19.5 Exception Trap
V850ES/JF3-L, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
19.5.1 Illegal opcode
23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B. When such an instruction is executed, an exception trap is
generated.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to
Caution It is recommended not to use an illegal opcode because instructions may newly be assigned in the
(1) Operation
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control.
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
The processing of the exception trap is shown below.
future.
×: Arbitrary
15
×
×
×
×
11
×
10
1
1
1
1
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
1
1
5
4
×
×
×
×
×
0
31
×
×
×
×
27 26
×
0
1
1
1
to
1
1
23 22
1
1
× × × × × × 0
16
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