UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 696

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Item
LVI
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP2, TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
Note Be sure to stop the PLL (PLLCTL.PLLON bit = 0).
Setting of Low-Voltage
CSIB0 to CSIB2
I
UARTA0 to UARTA2
2
C00 to I
Sub-IDLE Mode
2
Table 21-14. Operating Status in Low-Voltage Sub-IDLE Mode
C01
Operable
Oscillates
Oscillation enabled
Stops operation
Stops operation
Stops operation
Stops operation (but standby mode release is possible)
Stops operation
Stops operation
Operable when f
Operable when f
Operable when f
Stops operation
(When the SCKBn input clock is selected as the count clock, be sure to stop the
SCKBn input clock (n = 0 to 2).)
Stops operation
Stops operation
(When the ASCKA0 input clock to UARTA0 is selected, be sure to stop the ASCKA0
input clock.)
Stops operation
Stops operation (must stop)
Stops operation (output held)
Operable
Stops operation
See 2.2 Pin States (same operation status as IDLE1 and IDLE2 modes).
Retains status before low-voltage sub-IDLE mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the low-voltage sub-IDLE mode
was set.
Note
R
XT
R
/8 or f
/8 or f
is selected as the count clock
Main Clock Is Stopped (Must Be Stopped)
XT
XT
is selected as the count clock
is selected as the count clock
Operating Status
CHAPTER 21 STANDBY FUNCTION
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