UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 740

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
28.4.4 Selection of communication mode
switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
In the V850ES/JF3-L, the communication mode is selected by inputting pulses (11 pulses max.) to the FLMD0 pin after
The following shows the relationship between the number of pulses and the communication mode.
Note The number of clocks is as follows depending on the communication mode.
Caution
0
8
11
Other
TXDA0 (output)
FLMD0 Pulse
RESET (input)
FLMD1 (input)
FLMD0 (input)
RXDA0 (input)
When UARTA0 is selected, the receive clock is calculated based on the reset command sent
from the dedicated flash programmer after receiving the FLMD0 pulse.
V
DD
UARTA0
CSIB0
CSIB0 + HS
RFU
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
Communication Mode
Power on
Figure 28-8. Selection of Communication Mode
released
Reset
Oscillation
stabilized
Communication rate: 9,600 bps (after reset), LSB first
V850ES/JF3-L performs slave operation, MSB first
V850ES/JF3-L performs slave operation, MSB first
Setting prohibited
Communication
mode selected
(Note)
Flash control command communication
Remarks
CHAPTER 28 FLASH MEMORY
(erasure, write, etc.)
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