PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 102
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PIC17C756-16/SP
Manufacturer Part Number
PIC17C756-16/SP
Description
MICRO CTRL 16K MEMORY OTP 64SDIP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-16/SP
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-SDIP (0.750", 19.05mm)
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
PIC17C756-16/P
Available stocks
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Manufacturer:
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- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 102 of 321
- Download datasheet (3Mb)
13.2.2
This mode is selected by setting bit CA1/PR3. A block
diagram is shown in Figure 13-9. In this mode, TMR3
runs without a period register and increments from
0000h to FFFFh and rolls over to 0000h. The TMR3
interrupt Flag (TMR3IF) is set on this rollover. The
TMR3IF bit must be cleared in software.
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set upon detection of the capture event. The
corresponding interrupt mask bit is CA1IE. The
Capture1 Overflow Status bit is CA1OVF.
FIGURE 13-9: TIMER3 WITH FOUR CAPTURES BLOCK DIAGRAM
DS30264A-page 102
RB5/TCLK3
RB0/CAP1
RB1/CAP2
RG4/CAP3
RE3/CAP4
FOUR CAPTURE MODE
Fosc/4
TMR3CS
(TCON1<2>)
Edge Select,
Prescaler Select
Edge Select,
Prescaler Select
Edge Select,
Prescaler Select
Edge Select,
Prescaler Select
2
2
2
2
0
1
CA3ED1: CA3ED0
(TCON3<2:1>)
CA4ED1: CA4ED0
(TCON3<4:3>)
CA2ED1, CA2ED0
(TCON1<7:6>)
CA1ED1, CA1ED0
(TCON1<5:4>)
TMR3ON
(TCON2<2>)
Preliminary
Capture1 Enable
Capture2 Enable
Capture3 Enable
Capture4 Enable
Set CA1IF
Set CA2IF
Set CA3IF
Set CA4IF
(PIR2<2>)
(PIR2<3>)
(PIR1<2>)
(PIR1<3>)
PR3H/CA1H
CA2H
CA3H
CA4H
All the captures operate in the same manner. Refer to
Section 13.2.1 for the operation of capture.
PR3L/CA1L
CA2L
CA3L
CA4L
TMR3H
1997 Microchip Technology Inc.
TMR3L
Set TMR3IF
(PIR1<6>)
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