PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 305

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

F
Family of Devices
FERR ................................................................................ 115
Flowcharts
FOSC0 .............................................................................. 177
FOSC1 .............................................................................. 177
FS0 ............................................................................. 47, 274
FS1 ............................................................................. 47, 274
FS2 ............................................................................. 47, 274
FS3 ............................................................................. 47, 274
FSR0 ............................................................................. 44, 51
FSR1 ............................................................................. 44, 51
Fuzzy Logic Dev. System ( fuzzy TECH -MP) .......... 219, 221
G
GCE .................................................................................. 126
General Call Address Sequence....................................... 139
General Call Address Support .......................................... 139
General Call Enable bit, GCE ........................................... 126
General Format for Instructions ........................................ 184
General Purpose RAM........................................................ 39
General Purpose RAM Bank............................................... 53
General Purpose Register (GPR) ....................................... 42
GLINTD......................................................... 35, 48, 101, 180
Global Interrupt Disable bit, GLINTD .................................. 35
GOTO ............................................................................... 198
GPR (General Purpose Register) ....................................... 42
GPR Banks ......................................................................... 53
Graphs
1997 Microchip Technology Inc.
PIC12CXXX .............................................................. 293
PIC14C000 ............................................................... 293
PIC16C15X ............................................................... 294
PIC16C55X ............................................................... 296
PIC16C5X ................................................................. 295
PIC16C62X and PIC16C64X .................................... 296
PIC16C6X ................................................................. 297
PIC16C7XX............................................................... 298
PIC16C8X ................................................................. 299
PIC16C9XX............................................................... 300
PIC17C75X ................................................................... 6
PIC17CXX................................................................. 301
Acknowledge............................................................. 156
Master Receiver........................................................ 153
Master Transmit ........................................................ 150
Restart Condition ...................................................... 147
Start Condition .......................................................... 145
Stop Condition .......................................................... 158
I
I
I
I
Maximum I
125 C to -40 C) ........................................................ 253
Maximum I
Maximum I
RC Oscillator Frequency vs. V
RC Oscillator Frequency vs. V
RC Oscillator Frequency vs. V
Transconductance of LF Oscillator vs.V
Transconductance of XT Oscillator vs. V
Typical I
Typical I
Typical I
Typical RC Oscillator vs. Temperature ..................... 249
V
vs. V
V
OH
OH
OL
OL
IH
TH
, V
vs. V
vs. V
vs. V
vs. V
(Input Threshold Voltage) of I/O Pins vs. V
DD
IL
...................................................................... 259
of MCLR, T0CKI and OSC1 (In RC Mode)
DD
PD
PD
OL
OL
OH
OH
, V
, V
DD
PD
PD
vs. Frequency (External Clock 25 C) ..... 253
vs. V
vs. V
, V
, V
DD
DD
vs. Frequency (External Clock
vs. V
vs. V
DD
DD
DD
DD
= 3V ............................................... 257
= 5V ............................................... 258
= 3V .............................................. 256
= 5V .............................................. 257
DD
DD
Watchdog Disabled 25 C .......... 254
Watchdog Enabled 25 C ........... 255
Watchdog Disabled ............... 254
Watchdog Enabled................ 255
DD
DD
DD
(Cext = 100 pF).... 250
(Cext = 22 pF)...... 250
(Cext = 300 pF).... 251
DD
DD
............... 252
.............. 252
DD
... 258
Preliminary
H
Hardware Multiplier..............................................................61
I
I/O Ports
I
I
I
I
I
I
2
2
2
2
2
2
C .................................................................................... 134
C Master Mode Receiver Flowchart............................... 153
C Master Mode Reception ............................................. 152
C Master Mode Restart Condition.................................. 146
C Mode Selection........................................................... 134
C Module
V
Input (In XT, HS, and LP Modes) vs. V
WDT Timer Time-Out Period vs. V
Bi-directional................................................................83
I/O Ports ......................................................................65
Programming Considerations ......................................83
Read-Modify-Write Instructions ...................................83
Successive Operations................................................83
Addressing I
Arbitration ................................................................. 270
Combined Format..................................................... 269
I
Initiating and Terminating Data Transfer .................. 267
Master-Receiver Sequence ...................................... 269
Master-Transmitter Sequence .................................. 269
Multi-master.............................................................. 270
START...................................................................... 267
STOP................................................................ 267, 268
Transfer Acknowledge.............................................. 268
Acknowledge Flowchart............................................ 156
Acknowledge Sequence timing ................................ 155
Addressing................................................................ 135
Baud Rate Generator ............................................... 143
Block Diagram .......................................................... 141
BRG Block Diagram ................................................. 143
BRG Reset due to SDA Collision ............................. 162
BRG Timing .............................................................. 143
Bus Arbitration .......................................................... 160
Bus Collision............................................................. 160
Bus Collision timing .................................................. 160
Clock Arbitration ....................................................... 159
Clock Arbitration Timing (Master Transmit) .............. 159
Conditions to not give ACK Pulse............................. 135
General Call Address Support.................................. 139
Master Mode............................................................. 141
Master Mode 7-bit Reception timing......................... 154
Master Mode Operation............................................ 142
Master Mode Start Condition.................................... 144
Master Mode Transmission ...................................... 149
Master Mode Transmit Sequence ............................ 142
Master Transmit Flowchart ....................................... 150
Multi-Master Communication.................................... 160
Multi-master Mode.................................................... 142
Operation.................................................................. 134
Repeat Start Condition timing................................... 146
Restart Condition Flowchart ..................................... 147
Slave Mode............................................................... 135
2
TH
C Overview ............................................................ 267
(Input Threshold Voltage) of OSC1
Acknowledge .................................................... 160
Restart Condition.............................................. 163
Restart Condition Timing (Case1) .................... 163
Restart Condition Timing (Case2) .................... 163
Start Condition.................................................. 161
Start Condition Timing .............................. 161, 162
Stop Condition .................................................. 164
Stop Condition Timing (Case1) ........................ 164
Stop Condition Timing (Case2) ........................ 164
Transmit Timing................................................ 160
2
C Devices............................................ 268
DD
DS30264A-page 305
....................... 256
DD
................ 259