PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 149

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

15.2.9
Transmission of a data byte, a 7-bit address, or the
either half of a 10-bit address is accomplished by sim-
ply writing a value to SSPBUF register. This action will
set the buffer full flag (BF) and allow the baud rate
generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time spec).
for one baud rate generator roll over count (T
Data should be valid before SCL is released high (see
Data setup time spec). When the SCL pin is released
high, it is held that way for T
pin must remain stable for that duration and some hold
time after the next falling edge of SCL.
eighth bit is shifted out (the falling edge of the eighth
clock), the BF flag is cleared and the master releases
SDA allowing the slave device being addressed to
respond with an ACK bit during the ninth bit time, if an
address match occurs or if data was received properly.
The status of ACK is read into the SSPCON2 register
bit6 on the falling edge of the ninth clock. If the master
receives an acknowledge, the acknowledge status bit
(AKSTAT) is cleared. If not, the bit is set. After the
ninth clock the SSPIF is set, and the master clock
(baud rate generator) is suspended until the next data
byte is loaded into the SSPBUF leaving SCL low and
SDA unchanged. (Figure 15-29)
1997 Microchip Technology Inc.
I
2
C MASTER MODE TRANSMISSION
BRG
, the data on the SDA
SCL is held low
After the
BRG
Preliminary
).
15.2.9.1
In transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
15.2.9.2
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
15.2.9.3
In transmit mode, the AKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0), and
acknowledge (ACK = 1). A slave sends an acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
BF STATUS FLAG
WCOL STATUS FLAG
AKSTAT STATUS FLAG
is set when the slave does not
DS30264A-page 149