PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 313

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

Figure 10-1:
Figure 10-2:
Figure 10-3:
Figure 10-4:
Figure 10-5:
Figure 10-6:
Figure 10-7:
Figure 10-8:
Figure 10-9:
Figure 10-10: Block Diagram of RD7:RD0 Port Pins
Figure 10-11: Block Diagram of RE2:RE0 (in I/O Port
Figure 10-12: Block Diagram of RE3/CAP4 Port Pin ........ 77
Figure 10-13: Block Diagram of RF7:RF0......................... 78
Figure 10-14: Block Diagram of RG3:RG0........................ 80
Figure 10-15: RG4 Block Diagram .................................... 81
Figure 10-16: RG7:RG5 Block Diagram............................ 81
Figure 10-17: Successive I/O Operation ........................... 83
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 12-4:
Figure 12-5:
Figure 13-1:
Figure 13-2:
Figure 13-3:
Figure 13-4:
Figure 13-5:
Figure 13-6:
Figure 13-7:
Figure 13-8:
Figure 13-9:
Figure 13-10: Timer1, Timer2, and Timer3 Operation
Figure 13-11: Timer1, Timer2, and Timer3 Operation
Figure 14-1:
Figure 14-2:
Figure 14-3:
Figure 14-4:
Figure 14-5:
Figure 14-6:
Figure 14-7:
Figure 14-8:
Figure 14-9:
Figure 14-10: Synchronous Transmission
Figure 14-11: Synchronous Reception (Master Mode,
Figure 15-1:
Figure 15-2:
Figure 15-3:
Figure 15-4:
1997 Microchip Technology Inc.
RA0 and RA1 Block Diagram ..................... 65
RA2 Block Diagram .................................... 66
RA3 Block Diagram .................................... 66
RA4 and RA5 Block Diagram ..................... 66
Block Diagram of RB5:RB4 and RB1:RB0
Port Pins ..................................................... 68
Block Diagram of RB3:RB2 Port Pins......... 69
Block Diagram of RB6 Port Pin................... 70
Block Diagram of RB7 Port Pin................... 70
Block Diagram of RC7:RC0 Port Pins ........ 72
(in I/O Port Mode) ....................................... 74
Mode).......................................................... 76
T0STA Register (Address: 05h,
Unbanked) .................................................. 87
Timer0 Module Block Diagram ................... 88
TMR0 Timing with External Clock
(Increment on Falling Edge) ....................... 88
TMR0 Timing: Write High or Low Byte ....... 89
TMR0 Read/Write in Timer Mode ............... 90
TCON1 Register (Address: 16h, Bank 3) ... 91
TCON2 Register (Address: 17h, Bank 3) ... 92
TCON3 Register (Address: 16h, Bank 7) ... 93
Timer1 and Timer2 in Two 8-bit Timer/
Counter Mode ............................................. 94
TMR2 and TMR1 in 16-bit Timer/Counter
Mode........................................................... 95
Simplified PWM Block Diagram .................. 97
PWM Output ............................................... 97
Timer3 with three Capture and One
Period Register Block Diagram................. 100
Timer3 with Four Captures Block
Diagram .................................................... 102
(in Counter Mode)..................................... 104
(in Timer Mode) ........................................ 105
TXSTA1 Register (Address: 15h, Bank 0)
TXSTA2 Register (Address: 15h, Bank 4) 107
RCSTA1 Register (Address: 13h, Bank 0)
RCSTA2 Register (Address: 13h, Bank 4) 108
USART Transmit....................................... 109
USART Receive........................................ 109
Asynchronous Master Transmission......... 114
Asynchronous Master Transmission
(Back to Back) .......................................... 114
RX Pin Sampling Scheme ........................ 115
Asynchronous Reception.......................... 116
Synchronous Transmission ...................... 118
(Through TXEN) ....................................... 118
SREN)....................................................... 119
SPI Mode Block Diagram.......................... 123
I
I
SSPSTAT: Sync Serial Port Status
Register (Address: 13h, BANK 6) ............. 124
2
2
C Slave Mode Block Diagram ................ 123
C Master Mode Block Diagram .............. 123
Preliminary
Figure 15-5:
Figure 15-6:
Figure 15-7:
Figure 15-8:
Figure 15-9:
Figure 15-10: Slave Synchronization Timing .................. 131
Figure 15-11: SPI Mode Timing (Slave Mode with
Figure 15-12: SPI Mode Timing (Slave Mode with
Figure 15-13: SSP Block Diagram
Figure 15-14: I
Figure 15-15: I
Figure 15-16: I
Figure 15-17: I2C Slave-Transmitter (10-bit Address).... 137
Figure 15-18: I2C Slave-Receiver (10-bit Address)........ 138
Figure 15-19: General Call Address Sequence
Figure 15-20: SSP Block Diagram (I
Figure 15-21: Baud Rate Generator Block Diagram....... 143
Figure 15-22: Baud Rate Generator Timing With
Figure 15-23: First Start Bit Timing................................. 144
Figure 15-24: Start Condition FlowChart ........................ 145
Figure 15-25: Repeat Start Condition Timing ................. 146
Figure 15-26: Restart Condition FlowChart (page 1)...... 147
Figure 15-27: Restart Condition FlowChart (page 2)...... 148
Figure 15-28: Master Transmit FlowChart ...................... 150
Figure 15-29: I
Figure 15-30: Master Receiver FlowChart...................... 153
Figure 15-31: I
Figure 15-32: Acknowledge Sequence Timing ............... 155
Figure 15-33: Acknowledge FlowChart........................... 156
Figure 15-34: Stop Condition Receive or Transmit
Figure 15-35: Stop Condition FlowChart ........................ 158
Figure 15-36: Clock Arbitration Timing in Master
Figure 15-37: Bus Collision Timing for Transmit and
Figure 15-38: Bus Collision During Start Condition
Figure 15-39: Bus Collision During Start Condition
Figure 15-40: BRG Reset Due to SDA Collision During
Figure 15-41: Bus Collision During a Restart Condition
Figure 15-42: Bus Collision During Restart Condition
Figure 15-43: Bus Collision During a Stop Condition
Figure 15-44:
Figure 15-45: Sample device configuration for I
Figure 16-1:
Figure 16-2:
SSPCON1: Sync Serial Port Control
Register1 (Address 11h, BANK 6)............ 125
SSPCON2: Sync Serial Port Control
Register2 (Address 12h, BANK 6)........... 126
SSP Block Diagram (SPI Mode)............... 128
SPI Mode Timing (Master Mode) ............. 129
SPI Master/Slave Connection .................. 130
CKE = 0)................................................... 132
CKE = 1)................................................... 133
(I
(7-bit Address).......................................... 136
(7-bit Address).......................................... 136
(7 or 10-bit Mode)..................................... 139
Clock Arbitration ....................................... 143
7 or 10-bit Address).................................. 151
7-Bit Address)........................................... 154
Mode ........................................................ 157
Transmit Mode ......................................... 159
Acknowledge ............................................ 160
(SDA only) ................................................ 161
(SCL = 0) .................................................. 162
Start Condition.......................................... 162
(Case 1).................................................... 163
(Case 2).................................................... 163
(Case 1).................................................... 164
(Case 2).................................................... 164
ADCON0 Register (Address: 14h,
Bank 5) ..................................................... 167
ADCON1 Register (Address 15h,
Bank 5) ..................................................... 168
2
2
2
2
2
Bus Collision During a Stop Condition
2
C Master Mode Block Diagram.............. 134
C Waveforms for Reception
C Waveforms for Transmission
C Master Mode Timing (Transmission,
C Master Mode Timing (Reception
C Mode)................................................ 134
2
C Master Mode) ... 141
DS30264A-page 313
2
C bus .. 165