PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 93
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PIC17C756-16/SP
Manufacturer Part Number
PIC17C756-16/SP
Description
MICRO CTRL 16K MEMORY OTP 64SDIP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-16/SP
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
64-SDIP (0.750", 19.05mm)
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
PIC17C756-16/P
Available stocks
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- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 93 of 321
- Download datasheet (3Mb)
FIGURE 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7)
1997 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5:
bit 4-3: CA4ED1:CA4ED0: Capture4 Mode Select bits
bit 2-1: CA3ED1:CA3ED0: Capture3 Mode Select bits
bit 0:
U-0
-
Unimplemented: Read as ‘0’
CA4OVF: Capture4 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture4 registers
0 = No overflow occurred on Capture4 registers
CA3OVF: Capture3 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA3H:CA3L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture3 registers
0 = No overflow occurred on Capture3 registers
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
PWM3ON: PWM3 On bit
1 = PWM3 is enabled (The RG5/PWM3 pin ignores the state of the DDRG<5> bit)
0 = PWM3 is disabled (The RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)
CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
R - 0
R - 0
R/W - 0
R/W - 0
Preliminary
R/W - 0
R/W - 0
R/W - 0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Reads as ‘0’
-n = Value at POR reset
DS30264A-page 93
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