PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 48

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

7.2.2.2
The CPUSTA register contains the status and control
bits for the CPU. This register has a bit that is used to
globally enable/disable interrupts. If only a specific
interrupt is desired to be enabled/disabled, please refer
to the INTerrupt STAtus (INTSTA) register and the
Peripheral Interrupt Enable (PIE) registers. The
CPUSTA register also indicates if the stack is available
and contains the Power-down (PD) and Time-out (TO)
bits. The TO, PD, and STKAV bits are not writable.
These bits are set and cleared according to device
logic. Therefore, the result of an instruction with the
CPUSTA register as destination may be different than
intended.
FIGURE 7-7:
DS30264A-page 48
bit7
bit 7-6: Unimplemented: Read as '0'
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
U - 0
—
CPU STATUS REGISTER (CPUSTA)
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDT instruction
0 = A Watchdog Timer time-out occurred
PD: Power-down Status bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set by software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set by software after a Brown-out Reset occurs)
U - 0
stack overflow, only a device reset will set this bit)
—
CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
STKAV GLINTD
R - 1
R/W - 1
R - 1
TO
Preliminary
R - 1
PD
The POR bit allows the differentiation between a
Power-on Reset, external MCLR reset, or a WDT
Reset. The BOR bit indicates if a Brown-out Reset
occured.
R/W - 0
POR
Note 1: The BOR status bit is a don’t care and is
R/W - 0
BOR
not
brown-out circuit is disabled (when the
BODEN bit in the Configuration word is
programmed).
bit0
necessarily
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
Read as ‘0’
1997 Microchip Technology Inc.
0h (stack overflow).
predictable
if
the