PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 165

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

15.3
For standard-mode I
resistors R
ing parameters
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
The supply voltage limits the minimum value of resistor
R
at V
example, with a supply voltage of V
V
1.7 k
Figure 15-45. The desired noise margin of 0.1V
the low level, limits the maximum value of R
resistors are optional.
FIGURE 15-45: SAMPLE DEVICE CONFIGURATION FOR I
OL
p
1997 Microchip Technology Inc.
leakage current).
due to the specified minimum sink current of 3 mA
OL
NOTE: I
max = 0.4V at 3 mA, R
max = 0.4V for the specified output stages. For
V
Connection Considerations for I
Bus
DD
p
line to which the pull up resistor is also connected.
2
R
C devices with input levels related to V
s
as a function of R
in Figure 15-45 depends on the follow-
2
C bus devices, the values of
p min
SDA
SCL
= (5.5-0.4)/0.003 =
DD
R
p
= 5V+10% and
p
is shown in
DD
s
must have one common supply
. Series
R
2
p
DD
C
Preliminary
for
R
s
V
DD
DEVICE
R
+ 10%
s
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
imum value of R
(Figure 15-45).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I
This control ensures that the rise and fall times of the
SCL and SDA pins will meet the minimum require-
ments as specified in the I
operation.
2
C BUS
p
due to the specified rise time
2
C mode (master or slave).
C
2
C specification for 400 kHz
b
=10 - 400 pF
DS30264A-page 165