PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 186

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

TABLE 18-2:
DS30264A-page 186
Mnemonic,
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DAW
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVFP
MOVPF
MOVWF
MULWF
NEGW
NOP
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBWF
SUBWFB
SWAPF
TABLRD
TABLWT
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Work-
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruc-
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
ing register (WREG) is required to be affected, then f = WREG must be specified.
the LSB of the PC (PCL)
tion is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruc-
tion.
NOP is executed.
f,d
f,d
f,d
f,s
f,d
f
f
f
f,s
f,d
f,d
f,d
f,d
f,d
f,d
f,d
f,p
p,f
f
f
f,s
—
f,d
f,d
f,d
f,d
f,s
f,d
f,d
f,d
t,i,f
t,i,f
PIC17CXXX INSTRUCTION SET
Description
ADD WREG to f
ADD WREG and Carry bit to f
AND WREG with f
Clear f, or Clear f and Clear WREG
Complement f
Compare f with WREG, skip if f = WREG
Compare f with WREG, skip if f > WREG
Compare f with WREG, skip if f < WREG
Decimal Adjust WREG Register
Decrement f
Decrement f, skip if 0
Decrement f, skip if not 0
Increment f
Increment f, skip if 0
Increment f, skip if not 0
Inclusive OR WREG with f
Move f to p
Move p to f
Move WREG to f
Multiply WREG with f
Negate WREG
No Operation
Rotate left f through Carry
Rotate left f (no carry)
Rotate right f through Carry
Rotate right f (no carry)
Set f
Subtract WREG from f
Subtract WREG from f with Borrow
Swap f
Table Read
Table Write
Cycles
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2 (3)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
0000 111d ffff ffff
0001 000d ffff ffff
0000 101d ffff ffff
0010 100s ffff ffff
0001 001d ffff ffff
0011 0001 ffff ffff
0011 0010 ffff ffff
0011 0000 ffff ffff
0010 111s ffff ffff
0000 011d ffff ffff
0001 011d ffff ffff
0010 011d ffff ffff
0001 010d ffff ffff
0001 111d ffff ffff
0010 010d ffff ffff
0000 100d ffff ffff
011p pppp ffff ffff
010p pppp ffff ffff
0000 0001 ffff ffff
0011 0100 ffff ffff
0010 110s ffff ffff
0000 0000 0000 0000
0001 101d ffff ffff
0010 001d ffff ffff
0001 100d ffff ffff
0010 000d ffff ffff
0010 101s ffff ffff
0000 010d ffff ffff
0000 001d ffff ffff
0001 110d ffff ffff
1010 10ti ffff ffff
1010 11ti ffff ffff
MSb
16-bit Opcode
1997 Microchip Technology Inc.
LSb
Status
Affected
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
OV,C,DC,Z
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
C
Z
Z
Z
Z
Notes
3
6,8
2,6,8
2,6,8
3
6,8
6,8
6,8
6,8
1,3
3
1
1
7
5