PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 163

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

15.2.14.2 BUS COLLISION DURING A RESTART
During a RESTART condition, a bus collision occurs if:
a)
b)
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>,
and counts down to 0.
de-asserted, and when sampled high, the SDA pin is
sampled. If SDA is low, a bus collision has occurred
(i.e. another master is attempting to transmit a data
’0’). If however SDA is sampled high then the BRG is
FIGURE 15-41: BUS COLLISION DURING A RESTART CONDITION (CASE 1)
FIGURE 15-42: BUS COLLISION DURING RESTART CONDITION (CASE 2)
1997 Microchip Technology Inc.
A ’0’ is sampled on SDA when SCL goes from ’0’
to ’1’
SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
SDA
SCL
BCLIF
RSEN
S
SSPIF
SDA
SCL
RSEN
BCLIF
S
SSPIF
CONDITION
The SCL pin is then
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
Preliminary
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
reloaded and begins counting. If SDA goes from high
to low before the BRG times out, no bus collision
occurs, because no two masters can assert SDA at
exactly the same time.
If, however, SCL goes from high to low before the
BRG times out and SDA has not already been
asserted, then a bus collision occurs. In this case,
another master is attempting to transmit a data ’1’ dur-
ing the RESTART condition.
If at the end of the BRG time out both SCL and SDA
are still high, the SDA pin is driven low, the BRG is
reloaded, and begins counting.
count, regardless of the status of the SCL pin, the SCL
pin is driven low and the RESTART condition is com-
plete. (Figure 15-41)
T
Cleared in software
BRG
Interrupt cleared
in software
At the end of the
DS30264A-page 163