PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 123

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

15.0
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
Refer to Application Note AN578, "Use of the SSP
Module in the I
Figure 15-1, Figure 15-2, and Figure 15-3 show the
block diagrams for the three different modes of opera-
tion.
FIGURE 15-1: SPI MODE BLOCK
1997 Microchip Technology Inc.
SDO
SCK
SDI
SS
SYNCHRONOUS SERIAL
PORT (SSP) MODULE
2
Read
SS Control
C Multi-Master Environment."
SMP:CKE
Select
DIAGRAM
Edge
Enable
bit0
Select
Edge
SSPBUF reg
Data to TX/RX in SSPSR
Data direction bit
2
SSPSR reg
SSPM3:SSPM0
2
Clock Select
C)
4
2
Write
Prescaler
4, 16, 64
clock
shift
TMR2 output
data bus
Internal
2
T
OSC
Preliminary
FIGURE 15-2: I
FIGURE 15-3: I
SDA
SCL
SDA
SCL
Baud Rate Generator
SSPADD<6:0>
7
Read
Read
clock
clock
shift
shift
DIAGRAM
DIAGRAM
2
2
C SLAVE MODE BLOCK
C MASTER MODE BLOCK
MSb
MSb
Start and Stop bit
detect / generate
Stop bit detect
Match detect
SSPADD reg
Match detect
SSPADD reg
SSPBUF reg
SSPBUF reg
SSPSR reg
SSPSR reg
Start and
LSb
LSb
DS30264A-page 123
Write
Write
Clear/Set P, bits
(SSPSTAT reg)
(SSPSTAT reg)
and Set SSPIF
Set/Clear S bit
data bus
data bus
Internal
Internal
Set, Reset
S, P bits
Addr Match
Addr Match
and