PIC17C756-16/SP Microchip Technology, PIC17C756-16/SP Datasheet - Page 134

• Manufacturer Part Number: PIC17C756-16/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-16/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-16/P

15.2
The SSP module in I
ter and slave functions (including general call support)
and provides interrupts on start and stop bits in hard-
ware to determine a free bus (multi-master function).
The SSP module implements the standard mode spec-
ifications as well as 7-bit and 10-bit addressing.
Appendix E gives an overview of the I
tion.
FIGURE 15-13: SSP BLOCK DIAGRAM
FIGURE 15-14: I
DS30264A-page 134
SDA
SDA
SCL
Baud Rate Generator
SCL
SSPADD<6:0>
SSP I
7
2
Read
Read
clock
clock
shift
shift
C Operation
(I
DIAGRAM
2
2
C MASTER MODE BLOCK
MSb
MSb
2
C MODE)
Start and Stop bit
C mode fully implements all mas-
detect / generate
Stop bit detect
Match detect
SSPADD reg
Match detect
SSPADD reg
SSPBUF reg
SSPBUF reg
SSPSR reg
SSPSR reg
Start and
LSb
LSb
2
Write
Write
C bus specifica-
Clear/Set P, bits
(SSPSTAT reg)
(SSPSTAT reg)
and Set SSPIF
Set/Clear S bit
data bus
data bus
Internal
Internal
Set, Reset
S, P bits
Addr Match
Addr Match
and
Preliminary
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. Pins that are on PortA are automatically config-
ured when the I
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON1<5>).
The SSP module has six registers for I
These are the:
• SSP Control Register1 (SSPCON1)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
• SSP Address Register (SSPADD)
The SSPCON1 register allows control of the I
ation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open drain. These
pins are on PORTA and therefore there is no need to
program to be inputs.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON1<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
sible
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Master mode, clock = OSC/4 (SSPADD +1)
2
C mode is enabled. The SSP module
2
C mode, with the SSPEN bit set,
1997 Microchip Technology Inc.
2
C modes to be selected:
2
C operation.
2
C oper-