MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 133

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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9.3.3 Timer Input Capture 4/Output Compare 5 Register
Use TI4/O5 as either an input capture register or an output compare register, depending on the function
chosen for the PA3 pin. To enable it as an input capture pin, set the I4/O5 bit in the pulse accumulator
control register (PACTL) to logic level 1. To use it as an output compare register, set the I4/O5 bit to a
logic level 0. Refer to
9.4 Output Compare
Use the output compare (OC) function to program an action to occur at a specific time — when the 16-bit
counter reaches a specified value. For each of the five output compare functions, there is a separate
16-bit compare register and a dedicated 16-bit comparator. The value in the compare register is
compared to the value of the free-running counter on every bus cycle. When the compare register
matches the counter value, an output compare status flag is set. The flag can be used to initiate the
automatic actions for that output compare function.
To produce a pulse of a specific duration, write a value to the output compare register that represents the
time the leading edge of the pulse is to occur. The output compare circuit is configured to set the
appropriate output either high or low, depending on the polarity of the pulse being produced. After a match
occurs, the output compare register is reprogrammed to change the output pin back to its inactive level
at the next match. A value representing the width of the pulse is added to the original value, and then
written to the output compare register. Because the pin state changes occur at specific values of the
free-running counter, the pulse width can be controlled accurately at the resolution of the free-running
counter, independent of software latencies. To generate an output signal of a specific frequency and duty
cycle, repeat this pulse-generating procedure.
The five 16-bit read/write output compare registers are: TOC1, TOC2, TOC3, and TOC4, and the TI4/O5.
TI4/O5 functions under software control as either IC4 or OC5. Each of the OC registers is set to $FFFF
on reset. A value written to an OC register is compared to the free-running counter value during each
E-clock cycle. If a match is found, the particular output compare flag is set in timer interrupt flag register
1 (TFLG1). If that particular interrupt is enabled in the timer interrupt mask register 1 (TMSK1), an interrupt
is generated. In addition to an interrupt, a specified action can be initiated at one or more timer output
pins. For OC[5:2], the pin action is controlled by pairs of bits (OMx and OLx) in the TCTL1 register. The
output action is taken on each successful compare, regardless of whether or not the OCxF flag in the
TFLG1 register was previously cleared.
Freescale Semiconductor
Register name: Timer Input Capture 4/Output Compare 5 (High)
Register name: Timer Input Capture 4/Output Compare 5 (Low)
Reset:
Reset:
Read:
Read:
Write:
Write:
9.7 Pulse
Bit 15
Bit 7
Bit 7
Bit 7
1
1
Figure 9-7. Timer Input Capture 4/Output
Accumulator.
Bit 14
Bit 6
1
1
6
6
Compare 5 Register Pair (TI4/O5)
M68HC11E Family Data Sheet, Rev. 5.1
Bit 13
Bit 5
5
1
5
1
Bit 12
Bit 4
4
1
4
1
Address: $101F
Address: $101E
Bit 11
Bit 3
3
1
3
1
Bit 10
Bit 2
2
1
2
1
Bit 9
Bit 1
1
1
1
1
Bit 0
Bit 8
Bit 0
Bit 0
1
1
Output Compare
133

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