MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 142

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Timing Systems
9.5.2 Timer Interrupt Flag Register 2
Bits of this register indicate the occurrence of timer system events. Coupled with the four high-order bits
of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven
system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0] — Unimplemented
9.5.3 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits control the pulse
accumulator and IC4/OC5 functions.
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
142
Set when TCNT changes from $FFFF to $0000
The RTIF status bit is automatically set to 1 at the end of every RTI period. To clear RTIF, write a byte
to TFLG2 with bit 6 set.
Refer to
Refer to
Always read 0
Refer to
Refer to
Refer to
9.7 Pulse
9.7 Pulse
Chapter 6 Parallel Input/Output (I/O)
9.7 Pulse
9.7 Pulse
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 9-23. Pulse Accumulator Control Register (PACTL)
Accumulator.
Accumulator.
Accumulator.
Accumulator.
DDRA7
$1025
$1026
Bit 7
TOF
Bit 7
Figure 9-22. Timer Interrupt Flag 2 Register (TFLG2)
0
0
= Unimplemented
PAEN
RTIF
6
0
6
0
M68HC11E Family Data Sheet, Rev. 5.1
PAMOD
PAOVF
5
0
5
0
PEDGE
Ports.
PAIF
4
0
4
0
DDRA3
3
0
3
0
I4/O5
2
0
2
0
RTR1
1
0
1
0
Freescale Semiconductor
RTR0
Bit 0
Bit 0
0
0

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