MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 86

no-image

MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711E20CFN2
Manufacturer:
VISHAY
Quantity:
10 000
Part Number:
MC68HC711E20CFN2
Manufacturer:
FREESCAL
Quantity:
276
Part Number:
MC68HC711E20CFN2
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MC68HC711E20CFN2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC711E20CFN2
Manufacturer:
MOT
Quantity:
1 000
Resets and Interrupts
Any one of these interrupts can be assigned the highest maskable interrupt priority by writing the
appropriate value to the PSEL bits in the HPRIO register. Otherwise, the priority arrangement remains the
same. An interrupt that is assigned highest priority is still subject to global masking by the I bit in the CCR,
or by any associated local bits. Interrupt vectors are not affected by priority assignment. To avoid race
conditions, HPRIO can be written only while I-bit interrupts are inhibited.
5.4.1 Highest Priority Interrupt and Miscellaneous Register
RBOOT — Read Bootstrap ROM Bit
SMOD — Special Mode Select Bit
MDA — Mode Select A Bit
IRVNE — Internal Read Visibility/Not E Bit
PSEL[3:0] — Priority Select Bits
86
Has meaning only when the SMOD bit is a 1 (bootstrap mode or special test mode). At all other times
this bit is clear and cannot be written. Refer to
more information.
This bit reflects the inverse of the MODB input pin at the rising edge of reset. Refer to
Operating Modes and On-Chip Memory
The mode select A bit reflects the status of the MODA input pin at the rising edge of reset. Refer to
Chapter 2 Operating Modes and On-Chip Memory
The IRVNE control bit allows internal read accesses to be available on the external data bus during
operation in expanded modes. In single-chip and bootstrap modes, IRVNE determines whether the E
clock is driven out an external pin. For the MC68HC811E2, this bit is IRV and only controls internal
read visibility. Refer to
These bits select one interrupt source to be elevated above all other I-bit-related sources and can be
written only while the I bit in the CCR is set (interrupts disabled).
Reset:
1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the
Special test:
Single chip:
Expanded:
Bootstrap:
RESET pin rising edge. Refer to
Address:
Read:
Write:
RBOOT
$103C
Bit 7
Chapter 2 Operating Modes and On-Chip Memory
0
0
1
0
(1)
Figure 5-4. Highest Priority I-Bit Interrupt
SMOD
and Miscellaneous Register (HPRIO)
6
0
0
1
1
M68HC11E Family Data Sheet, Rev. 5.1
(1)
MDA
Table 2-1. Hardware Mode Select
for more information.
5
0
1
0
1
(1)
Chapter 2 Operating Modes and On-Chip Memory
IRVNE
4
0
0
0
1
for more information.
PSEL2
3
0
0
0
0
PSEL2
Summary.
2
1
1
1
1
for more information.
PSEL1
1
1
1
1
1
Freescale Semiconductor
PSEL0
Bit 0
0
0
0
0
Chapter 2
for

Related parts for MC68HC711E20CFN2