MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 146

no-image

MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Timing Systems
9.7.2 Pulse Accumulator Count Register
This 8-bit read/write register contains the count of external input events at the PAI input or the
accumulated count. The PACNT is readable even if PAI is not active in gated time accumulation mode.
The counter is not affected by reset and can be read or written at any time. Counting is synchronized to
the internal PH2 clock so that incrementing and reading occur during opposite half cycles.
9.7.3 Pulse Accumulator Status and Interrupt Bits
The pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF, are located within timer registers
TMSK2 and TFLG2.
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag
146
The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF to $00. To clear
this status bit, write a 1 in the corresponding data bit position (bit 5) of the TFLG2 register. The PAOVI
control bit allows configuring the pulse accumulator overflow for polled or interrupt-driven operation
and does not affect the state of PAOVF. When PAOVI is 0, pulse accumulator overflow interrupts are
inhibited, and the system operates in a polled mode, which requires that PAOVF be polled by user
software to determine when an overflow has occurred. When the PAOVI control bit is set, a hardware
interrupt request is generated each time PAOVF is set. Before leaving the interrupt service routine,
software must clear PAOVF by writing to the TFLG2 register.
Address:
Address:
Address:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 9-26. Pulse Accumulator Count Register (PACNT)
$1027
$1024
$1025
Bit 7
Figure 9-27. Timer Interrupt Mask 2 Register (TMSK2)
Bit 7
Bit 7
Bit 7
TOF
TOI
Figure 9-28. Timer Interrupt Flag 2 Register (TFLG2)
0
0
= Unimplemented
= Unimplemented
Bit 6
RTIF
RTII
6
6
0
6
0
M68HC11E Family Data Sheet, Rev. 5.1
PAOVF
PAOVI
Bit 5
5
5
0
5
0
Indeterminate after reset
Bit 4
PAIF
PAII
4
4
0
4
0
Bit 3
3
3
0
3
0
Bit 2
2
2
0
2
0
Bit 1
PR1
1
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 0
Bit 0
PR0
Bit 0
0
0

Related parts for MC68HC711E20CFN2