MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 51

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MC68HC711E20CFN2

Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E20CFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
PGM — EPROM Programming Voltage Enable Bit
2.5 EEPROM
Some E-series devices contain 512 bytes of on-chip EEPROM. The MC68HC811E2 contains 2048 bytes
of EEPROM with selectable base address. All E-series devices contain the EEPROM-based CONFIG
register.
2.5.1 EEPROM and CONFIG Programming and Erasure
The erased state of an EEPROM bit is 1. During a read operation, bit lines are precharged to 1. The
floating gate devices of programmed bits conduct and pull the bit lines to 0. Unprogrammed bits remain
at the precharged level and are read as ones. Programming a bit to 1 causes no change. Programming
a bit to 0 changes the bit so that subsequent reads return 0.
When appropriate bits in the BPROT register are cleared, the PPROG register controls programming and
erasing the EEPROM. The PPROG register can be read or written at any time, but logic enforces defined
programming and erasing sequences to prevent unintentional changes to EEPROM data. When the
EELAT bit in the PPROG register is cleared, the EEPROM can be read as if it were a ROM.
The on-chip charge pump that generates the EEPROM programming voltage from V
capacitors, which are relatively small in value. The efficiency of this charge pump and its drive capability
are affected by the level of V
of bits being programmed or erased and capacitances in the EEPROM array.
The clock source driving the charge pump is software selectable. When the clock select (CSEL) bit in the
OPTION register is 0, the E clock is used; when CSEL is 1, an on-chip resistor-capacitor (RC) oscillator
is used.
The EEPROM programming voltage power supply voltage to the EEPROM array is not enabled until there
has been a write to PPROG with EELAT set and PGM cleared. This must be followed by a write to a valid
EEPROM location or to the CONFIG address, and then a write to PPROG with both the EELAT and
EPGM bits set. Any attempt to set both EELAT and EPGM during the same write operation results in
neither bit being set.
2.5.1.1 Block Protect Register
This register prevents inadvertent writes to both the CONFIG register and EEPROM. The active bits in
this register are initialized to 1 out of reset and can be cleared only during the first 64 E-clock cycles after
reset in the normal modes. When these bits are cleared, the associated EEPROM section and the
CONFIG register can be programmed or erased. EEPROM is only visible if the EEON bit in the CONFIG
register is set. The bits in the BPROT register can be written to 1 at any time to protect EEPROM and the
CONFIG register. In test or bootstrap modes, write protection is inhibited and BPROT can be written
repeatedly. Address ranges for protected areas of EEPROM differ significantly for the MC68HC811E2.
Refer to
Freescale Semiconductor
PGM can be read any time and can be written only when ELAT = 1.
0 = Programming voltage to EPROM array disconnected
1 = Programming voltage to EPROM array connected
Figure
2-16.
DD
and the frequency of the driving clock. The load depends on the number
M68HC11E Family Data Sheet, Rev. 5.1
DD
uses MOS
EEPROM
51

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