MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 106
![IC MPU 66MHZ COLDFIRE 196-MAPBGA](/photos/13/93/139389/mcf5272vm66_sml.jpg)
MCF5272VM66
Manufacturer Part Number
MCF5272VM66
Description
IC MPU 66MHZ COLDFIRE 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VM66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Cpu Speed
66MHz
Embedded Interface Type
UART, QSPI, USB, TDM
Digital Ic Case Style
BGA
No. Of Pins
196
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
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Local Memory
The mapping of a given access into the SRAM uses the following algorithm to determine if the access hits
in the memory:
if (RAMBAR[0] = 1)
4.3.2.2
After a hardware reset, the contents of the SRAM module are undefined. The valid bit of RAMBAR is
cleared, disabling the module. If the SRAM needs to be initialized with instructions or data, the following
steps should be performed:
The ColdFire processor or an external BDM emulator using the debug module can perform this
initialization.
4.3.2.3
Depending on the configuration defined by RAMBAR, instruction fetch accesses can be sent to the SRAM
module, ROM module, and instruction cache simultaneously. If the access is mapped to the SRAM
module, it sources the read data, discarding the instruction cache access. If the SRAM is used only for data
operands, setting RAMBAR[SC,UC] lowers power dissipation by disabling the SRAM during all
instruction fetches. Additionally, if the SRAM holds only instructions, setting RAMBAR[SD,UD] reduces
power dissipation.
Consider the examples on
4-4
1. Load RAMBAR, mapping the SRAM module to the desired location.
2. Read the source data and write it to the SRAM. Various instructions support this function,
3. After data is loaded into the SRAM, it may be appropriate to load a revised value into RAMBAR
including memory-to-memory MOVE instructions and the MOVEM opcode. The MOVEM
instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this
opcode generally provides the best performance.
with new write-protect and address space mask attributes. These attributes consist of the
write-protect and address-space mask fields.
if (requested address[31:12] = RAMBAR[31:12])
SRAM Initialization
Programming RAMBAR for Power Management
if (address space mask of the requested type = 0)
MCF5272 ColdFire
Table 4-3
Table 4-3. Examples of Typical RAMBAR Settings
Access is mapped to the SRAM module
if (access = read)
if (access = write)
Instructions only
Data only
Both instructions and data
Data Contained in SRAM RAMBAR[7–0]
of typical RAMBAR settings:
®
Read the SRAM and return the data
if (RAMBAR[8] = 0)
else Signal a write-protect access error
Integrated Microprocessor User’s Manual, Rev. 3
Write the data into the SRAM
0x2B
0x35
0x21
Freescale Semiconductor
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